Globalfoundries Inc.

Globalfoundries U.S. Inc.

George Robert Mulfinger

Ryan W Sporer

Judson Robert Holt

Timothy James McArdle

Hui Zang

Peter Baars

Wei Hong

Liu Jiang

Rick J Carter

Hans-Jürgen Thees

Jan Höntschel

Yusheng Bian

Jagar Singh

Xusheng Kevin Wu

Yi Qi

Zhenyu Hu

Alexander M Derrickson

Scott Beasor

Jianwei Peng

Christopher D Sheraw

Matthew W Stoker

Alexander Lee Martin

Dina H Triyoso

Amy L Child

Hao Zhang

Yinxiao Yang

Lakshmanan H Vanamurthy

Mira Park

Ömür I Aydin

Ruilong Xie

Julien Frougier

Hong Yu

Shesh Mani Pandey

Jody Alan Fronheiser

Katherina E Babich

Daniel J Jaeger

Michael Vincent Aquilino

Mark V Raymond

Man Gu

El Mehdi Bazizi

Edmund Kenneth Banghart

Jin Zheng Wallner

Chung Foong Tan

Eric S Kozarsky

Steffen A Sichler

Kaustubh Shanbhag

Thomas Merbeth

Adam S Rosenfeld

Md Nasir Uddin Bhuyian

Selina A Mala

Disclosed are a semiconductor structure and method of forming the structure. The structure has a semiconductor layer. A gate structure is located on the semiconductor layer. The gate structure has a sidewall spacer having a first section on the semiconductor layer and positioned laterally adjacent to the gate structure and further having a second section above and wider than the first section and positioned laterally adjacent the gate structure. A source/drain region is on the semiconductor layer and positioned laterally adjacent to the first section and the second section of the sidewall spacer.

Structure and method of forming spacers on unfaceted raised source/drain regions

An integrated circuit (IC) device is disclosed which includes a first transistor over a substrate. The first transistor includes a gate over the substrate and between a source region and a drain region. The transistor further includes a first region of vertically-graded silicon germanium ('SiGe') adjacent a first side of a channel under the gate, and a second region of vertically-graded SiGe adjacent a second side of the channel. The channel includes substantially uniformly-graded SiGe.

IC device with vertically-graded silicon germanium region adjacent device channel and method for forming

Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Structure and method for random code generation

The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

Semiconductor structure with shared well

A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

Structure with different stress-inducing isolation dielectrics for different polarity FETs

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.

Asymmetrical lateral heterojunction bipolar transistors

Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

Field-effect transistors with diffusion blocking spacer sections

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

Lateral heterojunction bipolar transistors with asymmetric junctions

The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.

Silicided gate structures

One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

Formation of enhanced faceted raised source/drain EPI material for transistor devices

One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.

Formation of enhanced faceted raised source/drain epi material for transistor devices

The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

Faceted epitaxial source/drain regions

Growing community of inventors

Gansevoort, NY, United States of America

George Robert Mulfinger