Freescale Semiconductor,inc.

Nxp Usa, Inc.

George R Leal

Robert Joseph Wenzel

Marc Alan Mangrum

Jie-Hua Zhao

Scott M Hayes

Edward R Prack

David G Wontor

Brian D Sawyer

William H Lytle

Tim V Pham

Zhiwei Gong

Kevin John Hess

Trent Uehling

Douglas G Mitchell

Peter R Harper

Victor Adrian Chiriac

Craig S Amrine

Lizabeth Ann Keser

Tien Yu T Lee

Lois E Yong

Tu Anh Tran

Jeffrey W Metz

Dieu Van Dinh

Owen R Fay

Leo M Higgins, Iii

Scott K Pozder

Jason R Wright

Jianwen Xu

Wei Gao

Lakshmi Narayan Ramanathan

Betty H Yeung

Kevin J Hess

Trent S Uehling

A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.

Programmable stitch chaining of die-level interconnects for reliability testing

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids ().

Matrix lid heatspreader for flip chip package

Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

Method for singulating electronic components from a substrate

An electronic panel assembly (EPA) includes one or more electronic devices with primary faces having electrical contacts, opposed rear faces and edges therebetween. The devices are mounted primary faces down in openings in a warp control sheet (WCS). Cured plastic encapsulation is formed at least between lateral edges of the devices and WCS openings. Undesirable panel warping during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. Thin film insulators and conductors couple electrical contacts on various devices to each other and to external terminals, thereby forming an integrated multi-device EPA.

Warp compensated electronic assemblies

A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.

Methods and structures for reducing stress on die assembly

A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.

Recovery method for poor yield at integrated circuit die panelization

Methods and apparatus are provided for an electronic panel assembly (EPA) (), comprising: providing one or more electronic devices () with primary faces () having electrical contacts (), opposed rear faces () and edges () therebetween. The devices () are mounted primary faces () down on a temporary support () in openings () in a warp control sheet (WCS) () attached to the support (). Plastic encapsulation () is formed at least between lateral edges () of the devices () and WCS openings (). Undesirable panel warping () during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. After encapsulation cure, the EPA () containing the devices () and the WCS () is separated from the temporary support () and, optionally, mounted on another carrier () with electrical contacts () exposed. Thin film insulators () and conductors () are desirably applied to couple electrical contacts () on various devices () to each other and to external terminals (), thereby forming an integrated multi-device EPA ().

Warp compensated package and method

A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Fused buss for plating features on a semiconductor die

A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Method of forming a packaged semiconductor device

A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Circuit device with at least partial packaging and method for forming

A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

Method for controlling warpage in redistributed chip packaging panels

A package assemblyincludes a semiconductor die (e.g., an RF power amplifier)fixed within the cavity of a conductive leadframeusing a thermally and electrically-conductive adhesive material. The semiconductor diehas a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe)has two planar surfaces and a cavity formed therein. The adhesive materialis configured to couple the semiconductor diewithin the cavity of the conductive leadframesuch that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

Methods and apparatus for a semiconductor device package with improved thermal performance

A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. An encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.

Growing community of inventors

Cedar Park, TX, United States of America

George R Leal