Intel Corporation

Seeq Technology, Incorporated

George Perlegos

Phillip J Salsbury

George Smarandoiu

Mark A Holler

George J Korsh

Paolo Gargini

William S Johnson

Saroj Pathak

Anil Gupta

William L Morgan

Jerry Mar

Dov Frohman-Bentchkowsky

A memory array is organized into rows and columns of memory cells, each cell having a configuration which passes current or blocks current depending upon the state of that cell. The array includes sense circuits to sense cell state. In a preferred embodiment of the invention, an address signal sent to the memory array activates two sets of memory cells connected to the same sense lines, and the threshold level of the sense circuits is set above the level which would be sensed for a failed bit, so that a failed bit appears as if unprogrammed or erased. Because each bit is represented by a pair of memory cells, a failed cell in a pair will not affect operation of the functioning cell in the pair or result in error.

Fault-tolerant memory array

An MOS memory cell (44) including an electrically-programmable and electrically-erasable storage device (46) fabricated on a semiconductor substrate (50) is disclosed. The storage device (46) is divided into sensing and programming sections (90, 92), each of which sections comprises vertically-aligned floating gate and program gate portions (62L, 62R, 72L, 72R) respectively formed from first and second electrically-conductive strips (62, 72). A tunneling region (60) is formed in the substrate (50) beneath the floating gate portion (62R) of the storage device programming section (92) and a thin tunnel dielectric (70) is interposed between the tunneling region (60) and the programming section floating gate portion (62R to facilitate tunneling of charge carriers therebetween. First and second source/drain regions (94, 96) physically isolated from the tunneling region (60) are established in the substrate (50) in alignment with the sensing section floating gate and program gate portions (62L, 72L). The memory cell (44) additionally includes a selection device (48) comprised of first and second field effect transistor structures (98, 104) which can be activated during memory cell read, program and erase operations to supply selected unipolar potentials to the tunneling region (60) and the second source/drain region (96) associated with the storage device sensing section.

Electrically-programmable and electrically-erasable MOS memory device

A non-volatile memory cell circuit is used to replace a polysilicon fuse as an enabling element for a redundant row or column of memory cells in a semiconductor memory array. The fuse is divided into read and program sections, allowing a large device to be used for reading and a small device to be used for programming, thus permitting programming of all fuses in a redundant row simultaneously with minimal current consumption. The circuit may be embodied as a five-device or a four-device configuration.

Non-volatile memory cell fuse element

A semiconductor memory having back-up storage devices arranged along redundant word lines to replace defective storage devices located in the primary array of the memory. The memory includes a redundant decoder for enabling the redundant word lines in response to a selected address and a redundancy disable circuit for generating a signal indicative of redundant word line use.

Enabling circuit for redundant word lines in a semiconductor memory array

A sense amplifier (124) for use in determining the binary state of a selected storage device (4) in a semiconductor memory array (2) is disclosed. The sense amplifier (124) comprises a sensing section (150), a reference signal generator (148), and an inverting amplifier section (152). A relatively small current transistor (164) connected between a source of operating potential (158) and a voltage node (162) in the sensing section (150) supplies read currents to the selected storage device (4) via an enabled bit line (8) in the array (2). A second transistor (168) of relatively large size connected to the voltage node (162) in parallel with the current transistor (164) operates to rapidly raise the potential on the bit line (8) when the bit line (8) is first enabled. A third transistor (166) also of relatively large size connected between the voltage node (162) and the bit line (8) serves as a transfer gate for read currents. The reference signal generator (148) feeds a reference potential V.sub.ref to the control gates of the second and third transistors (168, 166), thereby establishing a quiescent bit line potential. The binary state of the selected storage device (4) can then be ascertained by sensing whether the voltage at the voltage node (162) drops in response to current flow through the enabled bit line (8) and selected storage device (4). Any voltage drop at the voltage node (162) which does occur is detected and amplified by the inverting amplifier section (152) of the sense amplifier.

Sense amplifier for use with a semiconductor memory array

An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.

Method of making EPROM cell with reduced programming voltage

Circuitry for isolating and rendering inoperative faulty storage devices in a semiconductor memory array is disclosed. A determination is made as to whether the x-addresses of the faulty storage devices contain an address bit having a common value for all of the faulty storage devices. If such an address bit exists, the address buffer associated with the common address bit is programmed to lock in a permanent set of address indicator outputs. All x-address locations accessed by address signals containing the common address bit are thereafter disabled. The memory array continues to function at half its former storage capacity, using the storage devices associated with the remaining address locations.

Electrical partitioning scheme for improving yields during the

EPROM Cell with reduced programming voltage and method of fabrication

An electrically alterable read-mostly MOS memory (commonly referred to as E.sup.2 PROM) employing floating gate memory devices is described. Each word stored in memory may be separately accessed for reading and writing. The memory array is arranged with additional lines and selection means to prevent the high-level programming signals from the X-decoders from programming all the floating gate devices along a selected X-line. A high voltage circuit is described which permits the handling of potentials greater than the grounded gate breakdown voltage associated with the shallow junction devices used in the memory. A unique sensing amplifier is also disclosed which detects low currents at high speeds.

Electrically alterable read-mostly memory

A metal-oxide-semiconductor (MOS) static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit may be laid-out along array lines where the lines have a pitch of approximately 12.25 microns. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.

MOS Static decoding circuit

An MOS sensing amplifier for sensing the binary state of floating gate memory devices in a read-only memory is disclosed. The potentials on the column lines in the memory are held to a narrow voltage swing. A pair of 'zero' threshold voltage transistors having slightly different threshold voltages are used to maintain the potentials on these lines. A potential developed from the column line is compared with a reference potential developed with a 'dummy' biasing network and a 'dummy' floating gate memory device.

Sensing amplifier for floating gate memory devices

An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 A-200 A) is used to separate this doped region from the floating gate. In one embodiment, a second layer of polysilicon is used to protect the thin oxide region during certain processing steps.

Electrically programmable and erasable MOS floating gate memory device

A floating gate storage device in which the channel is maintained at a first doping concentration to provide a low threshold voltage and preselected portions or regions along the sides of the channel are maintained at a second higher doping concentration to enhance programming of the device. These regions are formed as part of the 'front-end' processing of the substrate while forming channel stops, thus no additional processing is required.

Floating gate storage device and method of fabrication

An MOS buffer circuit which may be employed as part of a electrically programmable read-only memory or other MOS integrated circuit is described. The buffer may be 'powered down' when the memory is in a standby mode. Low threshold (zero threshold) voltage devices are employed in the circuit along with depletion mode transistors and enhancement mode transistors in a manner which permits the buffer to be readily powered down.

MOS Buffer circuit

A programmable and erasable MOS read-only memory employing floating gate memory cells. Unique, compact decoders allow the high voltage programming signal to be fully decoded without exposing the decoding transistors to the high voltage. The memory employs field-effect transistors having four different voltage thresholds. One such device is employed in the sense amplifiers to provide compensation for process variations and another device is used to allow the output buffers to be readily 'powered-down'.

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Fremont, CA, United States of America

George Perlegos