Infineon Technologies Ag

Qimonda Ag

Georg Erhard Eggers

Manfred Pröll

Stephan Schröder

Ralf Schneider

Herbert Benzinger

Jörg Kliewer

Christian Stocken

Johann Pfeiffer

Wolfgang Ruf

Stephan Schroeder

Manfred Proell

Manfred Dobler

Norbert Wirth

Joerg Kliewer

Thomas Huber

Jens Luepke

Eric Cordes

Arndt Gruber

Hartmut Berger

Kapil Gupta

Claus Peter

Hans-Joachim Kremer

Peggy Menck

Hermann Hass

An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs

Semiconductor memories () have segmented word lines (), which in each case have a main word line () made of a conductive metal and a plurality of interconnect segments () coupled to the main word line (), which are coupled to the respective main word line () in each case via at least one contact hole filling (). If one of the contact hole fillings () is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments () of two respective word lines () can be short-circuited in pairs with the aid of switching units (), whereby a static current (I) that flows via the contact hole fillings () can be used for electrically stressing the contact hole fillings (). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory

An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Integrated semiconductor memory and method for operating a semiconductor memory

A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Method and device for testing semiconductor memory devices

Performance Test Board for connecting at least one device under test (DUT) to a test system which has internal power supply sources (IPS) wherein said Performance Test Board (PTB) comprises at least one DC-DC-converter having an input terminal to which several internal power supply sources of said test system are connected in parallel, an output terminal to which a power supply terminal of said device under test (DUT) is connected and a control terminal to which a further internal power supply source of said test system is connected.

Performance test board

An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells

The invention involves a process for heating a semi-conductor component, as well as a semi-conductor component, whereby a device for heating the semi-conductor component is provided on the semi-conductor component.

Semiconductor component with internal heating

The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.

Apparatus for signaling that a predetermined time value has elapsed

A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.

Housing for semiconductor devices, semiconductor device pin, and method for the manufacturing of pins

An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Growing community of inventors

Munich, Germany

Georg Erhard Eggers