Advanced Micro Devices Corporation

Geoffrey Choh-Fei Yeap

Zoran Krivokapic

Ming-Ren Lin

Srinath Krishnan

Qi Xiang

Matthew S Buynoski

Akif Sultan

Che-Hoo Ng

Ognjen Milic

Shekhar Pramanick

Ognjen Milic-Strkalj

An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0&deg; to 60&deg; from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0&deg; to 60&deg; from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor

Semiconductor with laterally non-uniform channel doping profile

A semiconductor device having a transistor or capacitor with an ultra-thin oxide, which is thinner than 10 angstrom in thickness, is manufactured by eliminating a gate oxidation step in the processing and using the polysilicon reoxidation step to create the ultra-thin gate oxide by diffusion after formation of the gate.

Ultra-thin oxide for semiconductors

A method for fabricating a MOSFET device is provided. The method includes a step of forming a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.

Semiconductor device having enhanced gate capacitance by using both high

There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.

MOS device with self-compensating V.sub.aT -implants

An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

CMOS optimization method utilizing sacrificial sidewall spacer

Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich region generated when forming the LDD implant. Embodiments include ion implanting, Ge or Si to form surface amorphous and sub-surface, non-amorphous regions, and implanting B or BF.sub.2 to form the impurity region. Embodiments include forming the sub-surface, non-amorphous region before or after generating the surface amorphous region, and forming the impurity region before or after forming the sub-surface, non-amorphous region but after forming the surface amorphous region.

Formation of low resistance, ultra shallow LDD junctions employing a

A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.

Method for increasing gate capacitance by using both high and low

A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Ultra-shallow p-type junction having reduced sheet resistance and method

A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

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Sunnyvale, CA, United States of America

Geoffrey Choh-Fei Yeap