Taiwan Semiconductor Manufacturing Comp. Ltd.

Gene Wu

Jimmy Liang

Steven Hsu

Chien-Hsiun Lee

Tjandra Winata Karta

An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.

Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching

A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.

Packaging with base layers comprising alloy 42

A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.

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Dayuan, Taiwan

Gene Wu