International Business Machines Corporation

Gene T Patrick

John M Blondin

Steven Alan Cordes

S Jay Chey

Matthew J Farinelli

Sherif Ahmed Goma

Mohammed S Shaikh

Ronald Richard Breton

George W Twombly, Jr

Sami M Shaaban

Michael David Fregeau

Donald S Moran

Christopher J Ford

Michael F Beckett

Kevin M Potasiewicz

An apparatus for testing integrated circuit devices includes a probe device having a plurality of probes, a first substrate including a product substrate having a first surface and an array of electrical contacts disposed on the first surface thereof, and a second substrate disposed between the probes and the first substrate for electrically coupling the probes to corresponding electrical contacts disposed on the first surface of the product substrate.

Structure for coupling probes of probe device to corresponding electrical contacts on product substrate

An apparatus and a method for testing semiconductor devices such as integrated circuits having a handler for picking up an integrated circuit to be tested and placing the picked up integrated circuit into an automatic circuit test apparatus. When the circuit to be tested is inserted into the test apparatus an extraneous signal shield is automatically engaged to enclose the device being tested and protect the circuit, being tested, from stray extraneous electromagnetic signals during the test thereby preventing said stray electromagnetic interference from inducing errors in the tested circuit.

Apparatus for preventing cross talk and interference in semiconductor devices during test

A semi-conductor module burn-in test apparatus having a plurality burn-in boards each of which is provided a plurality of module test sockets thereon and each test socket is coupled to an adjacent test socket by with a high current, open/short split power connector that can readily connected to or disconnected from said adjacent test socket by coupling together the power inputs of the adjacent sockets or uncoupling the previously coupled power inputs of adjacent sockets and thereby selectively altering the current carrying levels available to said adjacent test sockets.

Semiconductor test and burn-in apparatus provided with a high current power connector for combining power planes

A method of and system for determining calibration offsets to account for delays introduced &ldquo;downstream&rdquo; of the reference driver ( ) of a tester system ( ) to test electronic components such as SRAM semiconductor memory devices. Such delays are created by, among other elements, receiver channels ( ) of the tester system. A plurality of calibration modules ( ) are provided, one for each receiver channel. Each calibration modules has a transmission line ( ) with a known delay, a first contact &prime; and a second contact &Prime;. The tester system includes a socket ( ) having a plurality of contactors ( ) for contacting the reference clock contact and data output contacts of the electronic components undergoing test. The first contact of each calibration module is positioned to engage the contactor that engages the reference clock contact of the electronic component. The second contact of each calibration module is positioned to engage a contactor that is different than the contactors that the second contacts of other calibration modules engage. Calibration offsets arising from delays introduced &ldquo;downstream&rdquo; of the tester system driver are determined for each receiver channel by subtracting the known delay for a calibration module associated with the receiver channel from the time between when (i) a test signal is provided by the reference driver at t and (ii) when the test signal is received at the receiver channel.

Calibration system and method for receiver guardband reductions

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Richmond, VT, United States of America

Gene T Patrick