Hefechip Corporation Limited

Silicon Storage Technology, Inc.

Apd Semiconductor, Inc.

Atmel Corporation

Diodes Inc.

Advanced Power Devices, Inc.

Other

Geeng-Chuan Chern

Vladimir Rodov

Paul C Chang

Wayne Y W Hsueh

Liang-Choo Hsia

Tsung-Ching Wu

Charles Lin

Philip S Ng

Jonathan Pabustan

Der-Tsyr Fan

Prateep Tuntasood

Steven J Schumann

Gary Michael Hurtz

Yaw Wen Hu

Ben Y Sheen

Ching-Lang Chiang

Jianren Bao

Prognyan Ghosh

Dana Lee

Amitay Levi

Chien-Sheng Su

Hidenori Akiyama

James C Hu

John Y Huang

Arthur Ching-Lang Chiang

Yasuo Ohtsuki

Haru Ohkawa

A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.

Trench capacitor having improved capacitance and fabrication method thereof

A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

Method for fabricating semiconductor memory device with buried capacitor and fin-like electrodes

A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Method of fabricating magnetic memory device

A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage

A semiconductor memory device includes at least an OTP cell having a transistor and a PN junction diode. The OTP cell further includes a substrate having a first conductivity type, and a source and a drain in the substrate. The source includes a source doping region having the first conductivity type. The drain includes a drain doping region having a second conductivity type opposite to the first conductivity type. A gate is disposed on the substrate between the source and the drain. The source further includes a pocket doping region having the second conductivity type under the gate. The pocket doping region and the source doping region constitute the PN junction diode.

One-time programmable memory device and fabrication method thereof

A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer.

Stacked capacitor with horizontal and vertical fin structures and method for making the same

A semiconductor device and methods thereof are disclosed. The proposed semiconductor device includes at least a unit cell wherein the unit cell includes a select transistor, and half of a ground-gate transistor electrically connected to the select transistor, and including a central conductive gate electrode region, two side conductive spacer regions and a gate dielectric layer, wherein a first and a second thicknesses of the gate dielectric layer underneath the two side conductive spacer regions are thinner than a third thickness of the gate dielectric layer underneath the central conductive gate electrode region.

1.5-transistor (1.5T) one time programmable (OTP) memory with thin gate to drain dielectric and methods thereof

A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

Semiconductor memory device with buried capacitor and fin-like electrodes

A magnetic memory device includes an MTJ element between a bottom electrode layer and a top electrode layer. The MTJ element comprises a reference layer, a tunnel barrier layer and a free layer. The reference layer comprises sub-layers that protrude beyond a sidewall of the tunnel barrier layer. The tunnel barrier layer protrudes beyond a sidewall of one of sub-layers of the free layer. Sidewall spacers are disposed to respectively cover a sidewall of the top electrode layer, sidewalls of the sub-layers of the free layer, a sidewall of the tunnel barrier layer, and sidewalls of the sub-layers of the reference layer. The etching of the MTJ stack and the formation of the sidewall spacers are carried out in the same HDPCVD chamber without breaking the vacuum.

Magnetic memory device with multiple sidewall spacers covering sidewall of MTJ element and method for manufacturing the same

Magnetic memory device and method for manufacturing the same

A MOS transistor includes a semiconductor substrate, a drain region and a source region in the semiconductor substrate, a channel region between the drain region and the source region, a gate electrode on the channel region, and a gate dielectric layer between the gate electrode and the semiconductor substrate. The gate dielectric layer has different thicknesses. The MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same

A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.

A semiconductor device includes at least a one-time programmable (OTP) physically unclonable function (PUF) unit cell with the PUF unit cell coupled to a bit line and a source line and includes an encode transistor is proposed. An encode enable transistor directly couples the bit line and the source line. A path programming the encode transistor is different from a path reading the encode transistor.

One time programmable (OTP) bits for physically unclonable functions

A semiconductor device includes a bottle-shaped capacitor cavity extends through a silicon device layer and a buried oxide layer of a substrate. The bottle-shaped capacitor cavity includes an upper portion in the silicon device layer and a widened bottom burrow in the buried oxide layer and underneath the silicon device layer. The widened bottom burrow is wider than the upper portion. A buried capacitor is disposed in the bottle-shaped capacitor cavity. The buried capacitor includes an inner electrode and an outer electrode with the capacitor dielectric layer therebetween. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode.

Semiconductor memory device with shallow buried capacitor and fabrication method thereof

A semiconductor device including at least an OTP unit cell is disclosed. The OTP unit cell includes a read select transistor, a data storage transistor serially connected to the read select transistor, and a program select transistor. The drain of the program select transistor is electrically coupled to the gate of the data storage transistor. The programming path for programming the three-transistor unit cell is different from the reading path for reading the OTP unit cell.

Growing community of inventors

Cupertino, CA, United States of America

Geeng-Chuan Chern