Intel Corporation

Gaurav Mehta

Sudarshan Kumar

Jiann-Cherng James Lan

Sadhana Madhyastha

Vivek Joshi

Wenjie Jiang

A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.

Low power precharge scheme for memory bit lines

A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

Method and apparatus for low power memory bit line precharge

A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

Multi-entry register cell

A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

Method and apparatus for low power domino decoding

A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors. Each of the sustainer circuits may include a pair of back-to-back inverters.

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Folsom, CA, United States of America

Gaurav Mehta