International Business Machines Corporation

Gary W Rubloff

Russell W Dreyfus

Johannes G Beha

Allan Mark Hartstein

Jeffrey Alan Kash

Paul S Ho

Gottlieb S Oehrlein

Peter O Hahn

Alfred Grill

Stephen McConnell Gates

Vishnubhai Vitthalbhai Patel

Rodney T Hodgson

Christoph S Harder

Joachim Gerhard Clabes

Donald R Young

Michael Liehr

Haralambos Lefakis

Karl Hofmann

Albertus Oosenbrug

Julian Juu-Chuan Hsieh

Marc F Wittmer

Harry Lefakis

Michel G Renier

Theodor Forster

System and method for controlling the thickness profile of deposited thin film layers over three-dimensional topography are disclosed, wherein low pressure chemical vapor deposition conditions are employed with the reactant beam collimated and chosen to impinge at a specific angle onto the surface, such that the reactive sticking coefficient s.sub.r with the deposition surface is &lt;1. Compared with conventional approaches, this method permits new shapes of the deposited thin film layer to be achieved over topography (such as trenches), including (i) tapered rather than re-entrant shapes (i.e., thicker at bottom rather than at top), (ii) enhanced sidewall and/or bottom coverage of trench structures (cf. the top surface), (iii) voidless, seamless filling of trench or via structures even at high aspect ratio (depth/width), and (iv) asymmetric sidewall coverage.

Apparatus for directional low pressure chemical vapor deposition (DLPCVD)

A method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The steps being: defining the position of the facets to be cleaved by scribing marks into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (l.sub.c) defining the length of the laser cavities and the distance (l.sub.b) between the facets of neighboring laser diodes; and covering the uppermost portion with an etch mask pattern which provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; and etching trenches into an upper portion of the structure defined by the etch windows; and partly underetching the upper portion during a second etch step such that the laser facets can be defined by cleaving the upper portion along the scribed marks without cleaving the whole laser structure; and ultrasonically or mechanically cleaving the upper portions being underetched along the scribed marks; and separating the laser diodes by cleaving them between neighboring lasers.

Full-wafer processing of laser diodes with cleaved facets

The invention provides a capacitor having increased capacitance comprising one or more main vertical trenches and one or more lateral trenches extending off the main vertical trench. The capacitor has alternating first and second regions, preferably silicon and non-silicon regions (for example, alternating silicon and germanium or alternating silicon and carbon regions). The etch characteristics of the alternating regions are utilized to selectively etch lateral trenches thereby increasing the surface area and capacitance of the capacitor. A method of fabricating the capacitors is also provided.

High area capacitor formation using material dependent etching

The invention provides a method of increasing the capacitance of a capacitor which comprises forming a capacitor having a main vertical trench and one or more lateral trenches extending off the main vertical trench. The capacitor has alternating first and second silicon regions, for example n-doped and p-doped silicon regions. After a main vertical trench is dry etched through the first and second silicon regions, the etch characteristics of the alternating first and second silicon regions are utilized to selectively dry etch lateral trenches, thereby increasing the surface area of the capacitor and the capacitance of the capacitor. Capacitors produced by this method are also provided.

High area capacitor formation using dry etching

A technique is described for improving metal-organic substrate adhesion and for reducing stress between the metal film and the substrate. Low energy reactive ions, electrons, or photons are incident upon the substrate to alter the surface chemistry of the substrate to a depth of from about 10 angstroms to a few hundred angstroms. The energy of the incident reactive ions and electrons is about 50-2000 eV, while the energy of the incident photons is about 0.2-500 eV. Irradiation of the substrate can occur prior to or during metal deposition. For simultaneous metal deposition/particle irradiation, the arrival rates of the metal atoms and the substrate treatment particles are within a few order of magnitude of one another. Room temperatures or elevated temperatures are suitable.

Metal-polymer adhesion by low energy bombardment

Contactless probing of an integrated circuit is carried out by flooding the surface of the integrated circuit with pulsed ultraviolet laser light, causing photoelectron emission as a function of the potentials at micropoints on the integrated circuit, converting this two-dimensional electron pattern into a corresponding relatively long duration pattern of luminescence by a luminescent target, and reviewing the result by video/computer scanning. Separate embodiments allow testing either in vacuum or in air, with or without insulating passivation layers present on the chip. The result is a contactless oscilloscope which monitors instantaneous voltages (logic states and AC switching waveforms) for a full two-demsnsional array of micropoints simultaneously. A chip with test points and appropriate windows for laser activation and luminescent targeting can be specially designed for optimal testing.

Full chip integrated circuit tester

An improved motive structure for transporting workpieces (wafers, chip, packages, etc.) between processing stations or tools in a manufacturing operation. The structure includes a first circular crankshaft assembly connected to center axles disposed at right angles to the transport motion. A second such crankshaft assembly is located some distance along the path of motion. Three driverods are connected between the first and second crankshaft assemblies, each affixed 120.degree. apart on the circular crankshafts so that each driverod is moved upward, then forward along the transport direction, then downward and backward to its original position as the crankshafts go through a complete 360.degree. rotation. The structure is disposed beneath transport rails which hold movable containers for holding the workpieces. As a driverod moves up and forward, it contacts a spring-loaded element on the movable container and drives it forward by friction contact. As each driverod begins to move down and away from the workpiece container, the next driverod is being rotated up and forward to continue to move the container along the rails. Pluralities of such structures are linearly arranged to provide an extended transport system.

Motive structure for transporting workpieces

Covering metal test pads of a passivated integrated circuit process intermediate wafer or completed integrated circuit chip-to-test, with a thin conductive overlayer, and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, provides a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads. The conductive overlayer may be removed after tests have been completed. Integrated circuit process intermediate chips may be specially designed for testability, with test sites grouped for easy access through windows left uncovered by subsequent layers.

Photon assisted tunneling testing of passivated integrated circuits

The insulating and stabiity characteristics of silicon dioxide gate oxide insulator for field effect transistors are enhanced by subjecting the silicon dioxide to an annealing in an ambient that contains a gaseous oxygen-containing species in an amount sufficient to provide a partial pressure from the oxygen-containing material of about 10.sup.-6 torr to about 10 torr during annealing temperatures of about 500.degree. C. to about 1200.degree. C. Such is carried out for a time sufficient to enhance the insulating and stability characteristics of the silicon dioxide insulator.

Post-oxidation anneal of silicon dioxide

A technique is described for increasing the adhesion between metals and organic substrates, where the metals are those which normally only very weakly bond to the substrate. These metals include Ni, Cu, Al, Ag, Au, Ta, Pt, Ir, Rh, Pd, Zn, and Cd. The organic substrates include mylar, polyimides, polyesters, polyethylene, polystyrene, etc. Enhanced adhesion occurs when intermixing between the depositing metal atoms and the substrate is optimized to a depth less than about 1000 angstroms into the substrate. This occurs in a critical substrate temperature range of about (0.6-0.8) T.sub.c, where T.sub.c is the curing temperature of the substrate. The deposition rate of the metal atoms is chosen such that the arrival rate of the metal atoms at the surface of the substrate is comparable to or less than the rate of diffusion of metal atoms into the substrate. This provides optimum intermixing and maximum adhesion.

Enhanced adhesion between metals and polymers

Testing of integrated circuit process intermediates, such as wafers, dise or chips in various stages of production (test chips) is facilitated by a nonintrusive, noncontact dynamic testing technique, using a pulsed laser, with laser light modification to increase photon energy through conversion to shorter wavelength. The high energy laser light excites electron emissions to pass to the detection system as a composite function of applied light energy and of dynamic operation of the circuit; detecting those emissions by an adjacent detector requires no ohmic contacts or special circuitry on the integrated circuit chip or wafer. Photoelectron energy emitted from a test pad on the test chip is detected as a composite function of the instantaneous input voltage as processed on the test chip, in dynamic operation including improper operation due to fault. The pulse from the laser, as modified through light modification, the parameters of detection of bias voltages, and the distances involved in chip-grid-detector juxtaposition, provides emissions for detection of circuit voltages occurring on the test chip under dynamic conditions simulating actual or stressed operation, with high time resolution of the voltages and their changes on the circuit.

Noncontact dynamic tester for integrated circuits

Contactless probing of an integrating circuit is carried out by flooding the surface of the integrated circuit with pulsed ultraviolet laser light, causing photoelectron emission as a function of the potentials at micropoints on the integrated circuit, converting this two-dimensional electron pattern into a corresponding relatively long duration pattern of luminescence by a luminescent target, and reviewing the result by video/computer scanning. Separate embodiments allow testing either in vacuum or in air, with or without insulating passivation layers present on the chip. The result is a contactless oscilloscope which monitors instantaneous voltage (logic states and AC switching waveforms) for a full two-dimensional array of micropoints simultaneously. A chip with test points and appropriate windows for laser activation and luminescent targeting can be specially designed for optimal testing.

A technique is described for producing very shallow doped regions in a substrate, at low temperatures. The doped regions are not in excess of about 300 angstroms in depth, and are formed at temperatures less than 700.degree. C. These shallow doped regions can be used in different applications, including the fabrication of semiconductor switching devices, diodes, and contacts. Overlayers containing the desired dopants are deposited on the substrate, after which an annealing step is carried out to institute the formation of a metallic compound. When the compound is formed, materials in the overlayers to be used as substrate dopants will be pushed ahead of the interface of the growing compound, and will be snowplowed into the top surface of the substrate, to produce the shallow doped region therein.

Low temperature shallow doping technique

Simultaneous noncontact testing of voltages across a full line of test sites on an integrated circuit chip-to-test is achieved with high time resolution using photoelectron emission induced by a pulsed laser focussed to a line on the chip-to-test, together with high speed electrostatic deflection perpendicular to the line focus. Photoelectrons produced by the line focus of pulsed laser light are imaged to a line on an array detector, the measured photoelectron intensities at array points along this line representing voltages at corresponding points along the line illuminated by the laser focus. High speed electrostatic deflection applied during the laser pulse, perpendicular to the direction of the line focus, disperses the line image (column) on the array detector across a sequence of sites at right angles (rows), thereby revealing the time-dependence of voltages in the column of test sites with high time resolution (in the picosecond range).

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Katonah, NY, United States of America

Gary W Rubloff