Micron Technology Incorporated

Other

Micron Semiconductor, Inc.

Gary R Gilliam

Roland Ochoa

Craig E Schneider

Kacey Cutler

Steve G Renfro

Kevin G Duesman

Leland R Nevill

Steven G Renfro

An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures. Performing chip testing with the substrate voltage level more positive than the normal negative voltage level facilitates detection of other margin failures and ion contamination.

On-chip substrate regulator test mode

An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes-wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures. Performing chip testing with the substrate voltage level more positive than the normal negative voltage level facilitates detection of other margin failures and ion contamination.

On-chip substrate regular test mode

A circuit for a sense amplifier (,) for use with a memory device (,). The circuit includes two devices (,and,) that are controlled by a selector (,). The first device (,) drives the sense amplifier (,) with a first current level. The second device (,) drives the sense amplifier (,) with a second current level, different from the first current level. The selector (,) is coupled to the first and second devices (,and,) so as to selectively couple one of the first and second devices (,and,) to the sense amplifier (,) based on a power supply voltage of the memory device (,).

Memory device with a sense amplifier

A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.

Circuit and method for enabling a function in a multiple memory device

A circuit for a sense amplifier (14) for use with a memory device (10). The circuts includes two devices(40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier(14) with a second current level, different from the first current level. The selector (14) is couple to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices(40and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

An apparatus, system and method for identifying an access mode of a semiconductor memory in a data processing system, characterized by significant reduction of the possibility of erroneous identification of the access mode. A semiconductor memory has an access circuit bank with plurality of selectable circuits only one of which is activated, each selectable circuit respectively associated with a selectable semiconductor memory access mode, the access mode selection typically being accomplished by selectively blowing fuses associated with the corresponding selectable circuits. A semiconductor memory access mode is correctly identified by associating, in response to a test signal for determining the fuse status, the respective activated selectable circuit with its corresponding access mode.

Apparatus, system and method for identifying semiconductor memory access

A circuit for testing for mobile ion contamination of a semiconductor chip has an enabling circuit, a voltage pump, and a regulating circuit. In a normal operating mode, the voltage pump is enabled whenever the substrate voltage drops below a normal operating voltage. In a test-mode, the voltage pump is continuously enabled to continually drive the substrate toward the normal operating voltage. However, the voltage regulating circuit is enabled to shunt current from the substrate to ground whenever the voltage pump drives the substrate beyond a test voltage that is intermediate the normal operating voltage and ground. The regulating circuit thus holds the substrate at the test voltage.

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Boise, ID, United States of America

Gary R Gilliam