International Business Machines Corporation

Gary L Patton

David Louis Harame

Johannes M Stork

Ramachandra Divakaruni

Arne Watson Ballantine

Douglas Duane Coolbaugh

Herbert Lei Ho

Bomy A Chen

Paul Christian Parries

Bernard S Meyerson

Ricky S Amos

Ernest Bassous

Heidi L Greer

Edward Kobeda

Emmanuel F Crabbe

Gregory Bazan

Joseph F Kudlacik

Bernard P Leroy

Maria C Stork

A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

Method of forming thermally stable polycrystal to single crystal electrical contact structure

A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

Graded bandgap single-crystal emitter heterojunction bipolar transistor

The present invention is directed to a method for forming a self-aligned epitaxial base transistor in a double polysilicon type process using non-selective low temperature epitaxy (LTE) to form the base layer. The present invention utilizes a thin very heavily doped LTE layer that is both a conductive etch stop and a diffusion source for doping the extrinsic base of the transistor. The deposition of the non-selective LTE base layer is followed immediately by the deposition of the conductive etch stop layer. A layer of undoped polycrystalline semiconductor is deposited on the conductive etch stop layer and subsequently ion implanted. Oxide and nitride insulating layers are deposited and the structure is patterned using a highly directional reactive ion etch to form the emitter window leaving a thin layer of the polycrystalline layer. The thin polycrystalline layer is selectively removed in a KOH solution leaving the conductive etch stop layer. The portion of the etch stop layer exposed in the emitter window is selectively removed by oxidation. Thereafter, conventional double polysilicon processing techniques are continued to form the insulator sidewalls and the emitter region in the window. During an annealing drive-in step, the conductive etch stop layer acts as an additional dopant source to the extrinsic base. The etch stop layer provides a conductive contact between the instrinsic base and the extrinsic base of the transistor.

Method for fabricating self-aligned epitaxial base transistor

A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.

Method for fabricating bipolar and CMOS devices in integrated circuits

A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etchig a shallow trench in the first layer and depositing semiconductor material of a second conductivity tyep by LTE and planarizing. The intrinsic regions for both of the transistors are formed by depositing a second layer of semiconductor material of the second conductivity type on the surface of the first layer and a third layer of semiconductor material of the first conductivity type on the surface of the second layer by either LTE or MBE. In one embodiment, the second and third layers are provided with a uniform vertical doping profile for one thickness of the layer and a graded doping profile for the remaining thickness in which the minimum doping level for both graded portions is at the junction between the second and third layers. The second layers forms the base and the third layer forms the collector for one transistor while at the same time the second layer forms a collector and the third layer forms the base for the other transistor. The performance of the intrinsic base and collector regions can be further improved by forming the second and third layers with a compound semiconductor material, such as, the compound of Si-Ge to create a heterojunction transistor. Device and intrinsic region isolation is effected by a combination of deep trench and shallow trench processes and reach-through regions for the sub-emitter and sub-collector are formed. A layer of polysilicon is deposited and selectively etched to form an extrinsic collector region for one transistor and extrinsic base regions for the other transistor. A further loayer of single crystal silicon is deposited to form the extrinsic base region for one transistor and the emitter for the other transistor.

Complementary bipolar transistor structure and method for manufacture

A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etching a shallow trench in the first layer and depositing semiconductor material of a second conductivity type by LTE and planarizing. The intrinsic regions for both of the transistors are formed by depositing a second layer of semiconductor material of the second conductivity type on the surface of the first layer and a third layer of semiconductor material of the first conductivity type on the surface of the second layer by either LTE or MBE. In one embodiment, the second and third layers are provided with a uniform vertical doping profile for one thickness of the layer and a graded doping profile for the remaining thickness in which the minimum doping level for both graded portions is at the junction between the second and third layers. The second layer forms the base and the third layer forms the collector for one transistor while at the same time the second layer forms a collector and the third layer forms the base for the other transistor. The performance of the intrinsic base and collector regions can be further improved by forming the second and third layers with a compound semiconductor material, such as, the compound of Si-Ge to create a heterojunction transistor. Device and intrinsic region isolation is effected by a combination of deep trench and shallow trench processes and reach-through regions for the sub-emitter and sub-collector are formed. A layer of polysilicon is deposited and selectively etched to form an extrinsic collector region for one transistor and extrinsic base regions for the other transistor. A further layer of single crystal silicon is deposited to form the extrinsic base region for one transistor and the emitter for the other transistor.

Complementary transistor structure and method for manufacture

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Poughkeepsie, NY, United States of America

Gary L Patton