International Business Machines Corporation

Other

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Siemens Corporation

Infineon Technologies North America Corp.

Siemens Microelectronics Limited

International Business Machines Coirporation

Infineon Technologies Ag

Qimonda Ag

Gary Bela Bronner

Jack Allan Mandelman

Carl John Radens

Ramachandra Divakaruni

Jeffrey P Gambino

Jochen C Beintner

Ulrike Gruening

David V Horak

Toshiharu Furukawa

Sang Hoo Dhong

Mary Elizabeth Weybright

Steven J Holmes

William R Tonti

Mark Charles Hakey

Wei Hwang

John Kenneth DeBrosse

David Edward Kotecki

Larry Alan Nesbit

Kangguo Cheng

Herbert Lei Ho

Byeong Yeol Kim

Johann Alsmeier

Devendra K Sadana

Ghavam G Shahidi

Louis L Hsu

Roy E Scheuerlein

Dureseti Chidambarrao

Wendell P Noble

James William Adkisson

Stephen McConnell Gates

Tze-Chiang Chen

Richard Anthony Conti

David M Dobuzinsky

Paul A Rabidoux

Dan Moy

Stephan Alan Cohen

Yujun Li

Bijan Davari

Donald J Samuels

Scott R Stiffler

Uwe Schroeder

Peter D Hoh

Karen P Madden

Wilfried Hansch

Oleg Gluschenkov

Son Van Nguyen

Haizhou Yin

Leland Chang

Laertis Economikos

Till Schloesser

Wilbur David Pricer

Bomy A Chen

Helmut Horst Tews

David Louis Harame

Rajarao Jammy

Wesley Charles Natzle

Viraj Yashawant Sardesai

Stanley Everett Schuster

David Michael Fried

Rama Divakaruni

Donald M Kenney

Stephan Kudelka

Bernard S Meyerson

Scott David Halle

Wolfgang Bergner

Byeongju Park

Gregory Costrini

Erick G Walton

Rajesh Rengarajan

Chienfan Yu

Badih El-Kareh

Dale Warner Martin

Erwin Hammerl

Alexander Michaelis

David C Ahlgren

Richard L Kleinhenz

Satish D Athavale

Rick L Mohler

Radhika Srinivasan

Junichiro Iba

Greg Costrini

Rainer F Schnabel

Ronald N Schulz

Bertrand Flietner

Yoichi Takegawa

Juergen Wittmann

Mark E Jost

John K Debrosse

Farid Agahi

Paul M Fahey

Ramachandra Divkaruni

Martin E Schrems

Stephen Kudelka

A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

Process for fabrication of FINFETs

A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

Conductive spacers for semiconductor devices and methods of forming

A method of fabricating a vertical field effect transistor ('FET') is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator ('SOI') region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

Method of fabricating vertical body-contacted SOI transistor

The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain

Process for fabrication of FinFETs

A vertical field effect transistor ('FET') is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator ('SOI') region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

Vertical body-contacted SOI transistor

The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

Out of the box vertical transistor for eDRAM on SOI

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain

In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.

DRAM cell with buried collar and self-aligned buried strap

A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI

The preferred embodiment of the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a &ldquo;lip&rdquo; at its top on the side the connection is to be made. To form the connection, dopant is diffused from the lower surface of the capacitor step and into the substrate, forming a surface strap to connect between the storage capacitor and the transfer device. This surface strap has the advantage of being self aligned with the storage capacitor and the transfer device, facilitating higher memory cell densities. The present invention can be used to form connections between storage capacitors and memory cells in a wide variety of devices.

Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby

A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

Self-aligned near surface strap for high density trench DRAMS

The distance between buried straps in a DRAM array of trench capacitor/vertical transistor cells is increased by offsetting adjacent cells by a vertical offset distance, so that the total distance between adjacent straps is increased without increasing the horizontal distance between cells.

DRAM having offset vertical transistors and method

A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

Grooved planar DRAM transfer device using buried pocket

Growing community of inventors

Stormville, NY, United States of America

Gary Bela Bronner