International Business Machines Corporation

Other

Infineon Technologies Ag

Infineon Technologies North America Corp.

Gangadhara Swami Mathad

Rajiv M Ranade

Lee Chen

Kevin K Chan

Munir D Naeem

Subhash Balakrishna Kulkarni

Madhav Datta

Siddhartha Panda

David Stanasolovich

Giorgio G Via

Tung J Chuang

Louis L Hsu

Rajiv V Joshi

Sampath Purushothaman

Hariklia Deligianni

Byeong Yeol Kim

Sung Kwon Kang

Leathen Shi

Ho-Ming Tong

Panayotis Constantinou Andricacos

Heon Lee

Thomas Safron Kanarsky

Wilma Jean Horkans

Shoaib Hasan Zaidi

Satish D Athavale

Keith Thomas Kwietniak

Young-Jin Park

Brian S Lee

Charles J Hendricks

Ravindra V Shenoy

John R Lankard

Syed Shoaib Hasan Zaidi

Pieter Geldermans

Stanley J Poloncic

Elizabeth Morales

Stephan P Kudelka

A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

Method to achieve increased trench depth, independent of CD as defined by lithography

There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A reflected light beam with respect to the planarized features is detected. Optical characteristics of the reflected light beam are analyzed to determine information corresponding to the planarized features. Preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a simplified geometry of the planarized features with respect to a geometry of similar, un-planarized features. Moreover, preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a reduction in complexity of the planarized features due to a similarity in refractive indexes corresponding to a bulk silicon substrate and a poly silicon fill of the semiconductor device.

Optical measurement of planarized features

A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.

Method for dry etching deep trenches in a substrate

The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Method to fill deep trench structures with void-free polysilicon or silicon

A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Method of etching high aspect ratio openings

A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.

Method to increase the etch rate and depth in high aspect ratio structure

A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate incident electromagnetic radiation having a wavelength above the wavelength at which the trenches act as waveguides for the radiation; collecting reflected electromagnetic radiation from the substrate; detecting a repetitive pattern of maximum intensities and minimum intensities of the reflected electromagnetic radiation during the etching; and determining the rate of etching based upon the wavelength of the incident electromagnetic radiation and the time period of the pattern.

Method for monitoring the rate of etching of a semiconductor

A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O , HBr and NF . An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O , HBr and SF or F .

Method of deep trench formation with improved profile control and surface area

Elimination/reduction of black silicon in DT etch

A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures.

Method of reducing RIE lag for deep trench silicon etching

An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

Flip-Chip interconnections using lead-free solders

A chemical etchant for the removal of titanium-tungsten containing structures from the semiconductors and a method for removing the titanium-tungsten. The etchant comprising a solution of hydrogen peroxide, a salt of EDTA, and an acid, the acid capable of preventing the deposition of tin oxide. The method of removal comprises first obtaining a wafer containing titanium-tungsten. Second, immersing the wafer having titanium-tungsten thereon for a predetermined period of time in an etchant bath comprising a solution of hydrogen peroxide, a salt of EDTA and an acid, the acid capable of preventing the deposition of tin oxide. Third, removing the treated wafer and rinsing the treated wafer and lastly, drying the wafer.

Etching of Ti-W for C4 rework

A sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions. The source/drain regions are formed by ion implantation using the expendable structure (diamond-like-carbon) as a mask. After the expendable structure has performed its further purpose of protecting the gate dielectric from contamination during the annealing cycle, the structure is easily removed by O.sub.2 plasma and replaced by a conventional metal gate material.

Formation of self-aligned metal gate FETs using a benignant removable

A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygenplasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrroldone (NMP).

Process of forming a dual overhang collimated lift-off stencil with

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Poughkeepsie, NY, United States of America

Gangadhara Swami Mathad