International Business Machines Corporation

Globalfoundries Inc.

Gangadhara Raja Muthinti

Andrew Mark Greene

Lawrence Alfred Clevenger

Benjamin David Briggs

Koichi Motoyama

Cornelius Brown Peethala

Michael Rizzolo

Ekmini Anuja De Silva

Yann Mignot

Marc Adam Bergendahl

Ravi K Bonam

Victor W C Chan

Matthew T Shoudy

Alex Joseph Varghese

Dallas M Lea

Ruqiang Bao

Gen Tsutsui

Chih-Chao Yang

Effendi Leobandung

Veeraraghavan S Basker

Junli Wang

Oscar Van Der Straten

Su Chen Fan

Kisik Choi

Nelson M Felix

Gauri V Karve

Scott David Halle

Matthew J Sendelbach

Shariq Siddiqui

Lisa F Edge

Siva Kanakasabapathy

Aron Cepler

Chiew-Seng Koay

Roy Koret

Wei Ti Lee

The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Secure fingerprinting of a trusted photomask

Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Semiconductor device with linerless contacts

A computer-implemented method for determining optical roughness in a semiconductor pattern structure that includes receiving, using a processor, optical responses spectra collected from the semiconductor pattern structure and constructing, using the processor optical critical dimension (OCD) models by using a set of input parameters for each layer of the semiconductor pattern structure. The method further includes calculating, using the processor, theoretical optical responses from a theoretical input generated by the OCD models. In addition, the method provides for comparing, using the processor, the optical responses spectra of the semiconductor pattern structure to the theoretical optical responses to determine output parameters for the optical roughness of the semiconductor pattern structure.

Determination of optical roughness in EUV structures

A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.

Single metallization scheme for gate, source, and drain contact integration

A computer-implemented method for measuring a parameter of a semiconductor. A non-limiting example of the computer-implemented method includes receiving, using a processor, a raw signal from a first tool representing a measured parameter of a semiconductor device. The method also receives, using the processor, data on the measured parameter from a second tool, and calculates, using the processor, the measured parameter based on the data received from the second tool and on a constraint based on the raw signal from the first tool.

Hybridization for characterization and metrology

Chamfer-less via interconnects and techniques for fabrication thereof with a protective dielectric arch are provided. In one aspect, a method of forming an interconnect includes: forming metal lines in a first dielectric; depositing an etch stop liner onto the first dielectric; depositing a second dielectric on the etch stop liner; patterning vias and a trench in the second dielectric, wherein the vias are present over at least one of the metal lines, and wherein the patterning forms patterned portions of the second dielectric/etch stop liner over at least another one of the metal lines; forming a protective dielectric arch over the at least another one of the metal lines; and filling the vias/trench with a metal(s) to form the interconnect which, due to the protective dielectric arch, is in a non-contact position with the at least another one of the metal lines. An interconnect structure is also provided.

Adjustable via dimension and chamfer angle

Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line Mto form a via V; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom

An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.

Multi-channel overlay metrology

A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.

Hybrid BEOL metallization utilizing selective reflection mask

Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.

Gate contact over active enabled by alternative spacer scheme and claw-shaped cap

Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

Gate cut critical dimension shrink and active gate defect healing using selective deposition

Integration of structures including an embedded magnetoresistive random access memory (MRAM) device such as a magnetic tunneling junction device includes pre-patterned etch stop layers to prevent excessive etching of the interlayer dielectric during a via open step.

Pre-patterned etch stop for interconnect trench formation overlying embedded MRAM structures

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Albany, NY, United States of America

Gangadhara Raja Muthinti