Globalwafers Co., Ltd.

Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Sunedison Semiconductor Limited (uen201334164h)

Taiwan Semiconductor Manufacturing Comp. Ltd.

Gang Wang

Shawn George Thomas

Jeffrey Louis Libbert

Igor Peidous

Srikanth Kommu

Qingmin Liu

Andrew Marquis Jones

Charles Robert Lottes

Sasha Joseph Kweskin

Lu Fei

Alex Usenko

Michael R Seacrist

Igor Rapoport

Jeffery L Libbert

Matty Caymax

Roger Loo

Niamh Waldron

Joshua Tseng

Benno Orschel

Arash Abedijaberi

Maarten Leys

Wei-e Wang

Ellen Torack

Andrew M Jones

Charles R Lottes

Charles Lottes

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

Methods for etching a semiconductor structure and for conditioning a processing reactor

Methods for conditioning a processing reactor

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

High resistivity semiconductor-on-insulator wafer and a method of manufacture

A preheat ring () for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.

CVD apparatus

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of SiGe, SiC, SiGeSn, SiGeSnC, GeSn, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

High resistivity SOI wafers and a method of manufacturing thereof

A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

A method is disclosed for promoting the formation of uniform platelets in a monocrystalline semiconductor donor substrate by irradiating the monocrystalline semiconductor donor substrate with light. The photon-absorption assisted platelet formation process leads to uniformly distributed platelets with minimum built-in stress that promote the formation a well-defined cleave-plane in the subsequent layer transfer process.

Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate

A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

High resistivity silicon-on-insulator structure and method of manufacture thereof

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

Methods for assessing semiconductor structures

A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um&#xd7;30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Manufacturing method of smoothing a semiconductor surface

Growing community of inventors

Grover, MO, United States of America

Gang Wang