Omnivision Technologies, Inc.

Magvision Semiconductor (beijing) Inc.

Meta Platforms Technologies, LLC

A9.com, Inc.

Silead Inc.

Gang Chen

Duli Mao

Dyson Hsinchih Tai

Hsin-Chih Tai

Hui Zang

Howard E Rhodes

Dajiang Yang

Vincent Venezia

Qin Wang

Yuanwei Zheng

Sing-Chung Hu

Yin Qian

Cunyu Yang

Chih-Wei Hsiung

Oray Orkun Cellek

Zhiqiang Lin

Lindsay Alexander Grant

Sohei Manabe

Keiji Mabuchi

Jin Li

Bill Phan

Arvind Kumar

Zhenhong Fu

Chen-Wei Lu

Min Hyuk Choi

Rongsheng Yang

Shiyu Sun

Ashish A Shah

Qianqian Wang

Guannan Chen

Yi Zhang

Yi Ma

Eric A G Webster

Johannes Solhusvik

Dominic Massetti

Trygve Willassen

Xianmin Yi

Lequn Liu

Dyson Hsin-Chih Tai

Keh-Chiang Ku

Bowei Zhang

Chao Niu

Zhibin Xiong

Xin Ru Wang

Boyd Fowler

Zhiming Zhuang

Chin Poh Pang

Yuanliang Liu

Wei Zheng

Chia-Chun Miao

Manoj Bikumandla

Takayuki Goto

Cheng Zhao

Jing Ye

Kenny Geng

Abraham Hossain Bagherjeiran

Philip John Cizdziel

Siguang Ma

Eric Webster

Jiaming Xing

Chiao-Ti Huang

Chein-Hsin Liu

Armin Yazdani

Fengyun Yan

Takeshi Takeda

Xi-Feng Gao

Hung Chih Chang

Zhi Hao

Dyson Hsinchin Tai

An image sensor device is disclosed. The image sensor device includes a number of pixels and neighboring pixels are isolated by deep trench isolation structures. In an embodiment, a method of forming a deep trench isolation structure includes performing a first etching process to remove a portion of a substrate, thereby forming a first trench in the substrate, performing a first doping process to form a first sidewall doped region along a sidewall surface of the first trench, after the performing of the first plasma doping process, performing a second etching process to extend the first trench, thereby forming a second trench in the substrate, and, after the performing of the second etching process, performing a second doping process to form a second sidewall doped region along a sidewall surface of the second trench, a portion of the second sidewall doped region overlaps with the first sidewall doped region.

Image sensor pixel with deep trench isolation structure

An image sensor device is disclosed. The image sensor device includes a substrate having a plurality of pixel regions. The image sensor device also includes a first photodiode in a first pixel region, a source follower transistor coupled to the first photodiode, and a select transistor coupled to the source follower transistor. One of the source follower transistor and the select transistor is in a second pixel region that is different from the first pixel region. While the source follower and the select transistor can be allocated to different cells, either the source follower or the select transistor or both can be further allocated or split into different cells.

Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.

Dual depth junction structures and process methods

A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.

Pixel cell having anti-blooming structure and image sensor

An image sensor device is disclosed. The image sensor device includes a substrate having a plurality of pixel regions. Two adjacent pixel regions are optically and electrically isolated by a deep trench isolation structure. In an embodiment, a method of forming the deep trench isolation structure includes receiving a workpiece comprising a first isolation structure formed in a front side of a substrate, forming a trench extending through the first isolation structure and the substrate, forming a dielectric liner to line the trench, depositing a conductive layer conformally over the workpiece after the forming of the dielectric liner, and depositing a dielectric fill layer over the conductive layer to fill the trench. A refractive index of the dielectric fill layer may be smaller than a refractive index of the conductive layer. The present disclosure also includes an alternative method for forming isolation structures at a back side of the substrate.

Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Uniform threshold voltage non-planar transistors

An image sensor device is disclosed. The image sensor device includes a substrate having a plurality of pixel regions. Two adjacent pixel regions are optically isolated by an isolation structure. In an embodiment, a method of forming the isolation structure includes receiving a workpiece having a first substrate, etching a frontside of the first substrate to form a first trench, depositing a fill layer in the first trench, removing a portion of the fill layer from the backside of the first substrate to form a second trench surrounded by the fill layer, and depositing a metal layer in the second trench to form the isolation structure.

Deep trench isolation structure for image sensor

Embodiments relate to a display device with subpixels that share switch transistors that selectively connect sources of driving transistors to a high voltage source. Further, part of reset transistors or part of a select transistor may be shared across multiple subpixels. The reset transistor selectively connects an anode of an organic light emitting diode (OLED) to a low voltage source. The select transistor selectively passes through pixel data from a data line when a gate signal is received via a gate line. Driver transistors and capacitors of the subpixels are independent and not shared. In this way, the dimensions of the subpixels may be reduced and enable increase in the density of the pixels.

Subpixels with reduced dimensions by using shared switching transistors

An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

Pixel layout with photodiode region partially surrounding circuitry

Embodiments relate to a display device including pixels that compensate a threshold voltage of a driving transistor using the body effect. Pixel data for the driving transistor increases the source-bulk voltage of the driving transistor during a compensation period as a result of the body effect. A separate reference voltage is not received at the pixel for the purpose of compensating the threshold voltage of the driving transistor. The increased source-bulk voltage is then used in an emission period of the pixel to compensate for the threshold voltage of the driving transistor.

Self-compensation of driving transistor threshold voltage using body effect

An uneven-trench pixel cell includes a semiconductor substrate that includes a floating diffusion region, a photodiode region, and, between a front surface and a back surface: a first sidewall surface, a shallow bottom surface, a second sidewall surface, and a deep bottom surface. The first sidewall surface and a shallow bottom surface define a shallow trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A shallow depth of the shallow trench exceeds a junction depth of the floating diffusion region. The second sidewall surface and a deep bottom surface define a deep trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A distance between the deep bottom surface and the front surface defines a deep depth, of the deep trench, that exceeds the shallow depth.

Uneven-trench pixel cell and fabrication method

Embodiments disclosed herein reduce petal flare. A flare-suppressing image sensor includes a plurality of pixels including a first set of pixels and a second set of pixels. The flare-suppressing image sensor further includes plurality of microlenses, where each microlens is aligned to a respective one of the first set of pixels. The flare-suppressing image sensor further includes plurality of sub-microlens, where each microlens array is aligned to a respective one of the second set of pixels.

Flare-suppressing image sensor

A pixel includes a semiconductor substrate, a low-&#x3ba; dielectric, and a photodiode region in the semiconductor substrate. The semiconductor substrate has a substrate top surface that forms a trench. The trench extends into the semiconductor substrate and has a trench depth relative to a planar region of the substrate top surface surrounding the trench. The low-&#x3ba; dielectric is in the trench between the trench depth and a low-&#x3ba; depth with respect to the planar region. The low-&#x3ba; depth is less than the trench depth. The photodiode region is in the semiconductor substrate and includes (i) a bottom photodiode section beneath the trench and (ii) a top photodiode section adjacent to the trench. The top photodiode section begins at a photodiode depth, with respect to the planar region, that is less than the low-&#x3ba; depth, and extends toward and adjoining the bottom photodiode section.

Pixel, associated image sensor, and method

A pixel-array substrate includes (i) a semiconductor substrate including a photodiode region and a floating diffusion region, and (ii) a vertical-transfer-gate structure that includes a trench and a gate electrode. The trench is defined by a bottom surface and a sidewall surface of the substrate each located between a front substrate-surface and a back substrate-surface thereof. The trench extends into the substrate. In a cross-sectional plane perpendicular to the front substrate-surface and intersecting the floating diffusion region, the photodiode region, and the sidewall surface, (a) the trench is located between the floating diffusion region and the photodiode region, and (b) a top section of the sidewall surface is adjacent to the floating diffusion region. A gate electrode partially fills the trench such that the top section and a conductive-surface of the gate electrode in-part define a recess located between the floating diffusion region and the gate electrode.

Pixel-array substrate

A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region.

Pointed-trench pixel-array substrate and associated fabrication method

Growing community of inventors

San Jose, CA, United States of America

Gang Chen