Intel Corporation

Gang Bai

Chunlin Liang

Brian S Doyle

David B Fraser

Peng Cheng

Jun-Fei Zheng

A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.

Multi-layer gate dielectric

A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Complementary metal gate electrode technology

A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

High dielectric constant metal oxide gate dielectrics

Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Method of making MOSFET gate electrodes with tuned work function

A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Method for tuning a work function for MOSFET gate electrodes

A MOSFET includes a double silicided source/drain structure wherein the source/drain terminals include a silicided source/drain extension, a deep silicided source/drain region, and a doped semiconductor portion that surrounds a portion of the source/drain structure such that the suicides are isolated from the MOSFET body node. In a further aspect of the present invention, a barrier layer is formed around a gate electrode to prevent electrical shorts between a silicided source/drain extension and the gate electrode. A deep source/drain is then formed, self-aligned to sidewall spacers that are formed subsequent to the silicidation of the source/drain extension.

Transistor structure having silicide source/drain extensions

The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.

Semiconductor device

A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.

Complementary metal gates and a process for implementation

Work function tuning for MOSFET gate electrodes

A method of fabricating an unlanded via over a polymer that is used as an intraline or intralayer dielectric is described. In one embodiment, the present invention creates an etch-stop layer for forming unlanded vias using three steps. A recess is created in an intraline dielectric, such as an organic polymer. An etch-stop layer is then deposited over the intraline dielectric. The etch-stop layer is then polished back before depositing a final insulating layer. The unlanded via is formed by etching through the final insulating layer. The intraline dielectric is protected by the etch-stop layer during the etch of the final insulating layer to form the unlanded via.

Unlanded vias with a low dielectric constant material as an intraline dielectric

A method for making a circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

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San Jose, CA, United States of America

Gang Bai