Lsi Logic Corporation

Gail D Shelton

Gayle W Miller

Brynne K Chisholm

Kunal N Taravade

A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.

Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device

A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

Method for enhancing anti-reflective coatings used in photolithography of electronic devices

A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.

Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint

An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatment oxidizes the implanted region.

Dual gate oxide process for deep submicron ICS

A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.

Method and apparatus for deposition of porous silica dielectrics

An apparatus for planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is disclosed. The apparatus is operable to detect the endpoint based upon the chemical slurry whether a catalytic reaction has occurred due to the polishing platen removing a portion of the catalyst material from the wafer.

Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material

The present invention provides bearing assemblies and methods of manufacturing bearing assemblies which allow for reliable, non-intrusive wear detection. In one embodiment, a bearing assembly (,) includes first and second bearing members (,) adapted for movement relative to each other. The first bearing member includes an outer layer (,) that is adapted to wear in response to the relative movement between bearing members, and an inner layer. The inner layer includes a base portion (,) having a first hardness and a plurality of spaced apart wear indicating regions (,) having a second hardness, whereby the first hardness and second hardness are different. The wear indicating regions are adapted to produce a vibration after sufficient wear of the outer layer.

High reliability bearing structure

Radio frequency photo conductive decay is used to monitor a small piece of high-grade silicon to determine if copper contamination has been removed from a probe tool. A probe tool is placed in contact with a small 'waferette' of silicon repeatedly until the copper signal is diminished, indicating that the tool may be used for other products without concern for copper contamination.

Copper contamination control of in-line probe instruments

A method of fabricating a semiconductor wafer is disclosed. The method includes the steps of (i) doping a resist substance with an electromagnetic radiation absorbing compound so as to form an electromagnetic radiation absorbing resist material, (ii) forming an electromagnetic radiation absorbing resist layer on a first side of the semiconductor wafer with the electromagnetic radiation absorbing material, (iii) subjecting the first side of the semiconductor wafer to an electromagnetic signal so that an amount of the electromagnetic signal is absorbed by the electromagnetic radiation absorbing compound present in the electromagnetic radiation absorbing resist layer such that an attenuated electromagnetic signal emanates from the semiconductor wafer, (iv) etching the first side of the semiconductor wafer during the subjecting step in order to remove a quantity of the electromagnetic radiation absorbing resist layer from the first side of the semiconductor wafer, (v) determining an intensity level of the attenuated electromagnetic signal, and (vi) stopping the etching step in response to the intensity level of the attenuated electromagnetic signal having a predetermined relationship with an intensity threshold level. An associated arrangement for etching a first side of a semiconductor wafer down to a desired level is also disclosed.

Method and arrangement for fabricating a semiconductor device

Endpoint detection method and apparatus which utilize a chelating agent

A method for composing a low dielectric thermally conductive thin film is disclosed. A layer of precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried and becomes a layer of porous silica film. Subsequently, the silicon substrate is exposed to a methane gas atmosphere at a temperature of approximately 200-350.degree. C., during which methane gas molecules are oxidized locally to liberate carbon atoms. Some of the liberated carbon atoms will bond to the interior of the porous silica film. The carbon atoms from the methane gas molecules then permeate the nanopores within the porous silica film such that the entire nanostructure of the porous silica film is carbidized. As a result, a composite porous silica film, which may serve as a dielectric layer within an interconnect structure, is formed.

Method for composing a thermally conductive thin film having a low

A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a sulfur-containing reporting specie includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method also includes the step of detecting presence of the sulfur-containing reporting specie in the material removed from the wafer. The method further includes the step of terminating the polishing step in response to detecting presence of the sulfur-containing reporting specie. A shallow trench isolation process for fabricating a semiconductor wafer is also disclosed.

Method of detecting a polishing endpoint layer of a semiconductor wafer

A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is discloes. One step of the method includes polishing a first side of the wafer in order to remove material from the wafer. Another step of the method includes determining that a catalytic reaction has occurred due to the polishing step removing the catalyst material of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the catalytic reaction has occurred. A polishing system is also disclosed which detects a polishing endpoint based upon a catalytic reaction triggered by a catalyst material of a polishing endpoint layer of a semiconductor device.

Growing community of inventors

Colorado Springs, CO, United States of America

Gail D Shelton