Texas Instruments Corporation

Gabriel George Barna

Olivier Alain Faynot

Andrew Marshall

Christoph A Wasshuber

James G Frank

Howard L Tigelaar

Brian Keith Kirkpatrick

Richard Gene Burch

Purnendu K Mozumder

Duane E Carter

Stephanie Watts Butler

Joseph C Davis

Demetre J Economou

David W Buck

Charles R Ratliff

David Anthony White

Donald A Sofge

Richard P VanMeurs

A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.

Recessed STI for wide transistors

A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned region offset by a non-selected region. The method also includes forming at least one quantum island from the thinned region by subjecting the thinned region to an annealing process. The non-selected region is aligned with the quantum island and tunnel junctions are formed between the quantum island and the non-selected region. The present invention also includes a single-electron device, and a method of manufacturing an integrated circuit that includes a single-electron device.

Method to manufacture silicon quantum islands and single-electron devices

A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through the first oxide layer and the nitride layer and into the substrate to create an isolation region, wherein the at least one trench is perpendicular to at least one gate structure in an active area of the substrate, layering the trench with a second oxide layer, removing the first oxide layer and second oxide layer, forming a third oxide layer on the planar substrate with recessed active trench, and forming the at least one circuitous gate structure on the third oxide layer connecting at least one electronic source and drain.

Transistors with recessed active trenches for increased effective gate width

A method () of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (), and forming an insulator layer on a second wafer (). The second wafer is treated () to generate a structural weakness therein, and the first and second wafers together () are then bonded together so that the channels face the insulator layer. A portion of the second wafer is then removed () from the bonded first and second wafers at a location corresponding to the structure weakness.

SOI wafer with cooling channels and a method of manufacture thereof

A method () of forming fully-depleted () and partially-depleted () silicon-on-insulator (SOI) devices on a single die in an integrated circuit device () is disclosed using SOI starting material () and a selective epitaxial growth process ().

Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices

The present invention provides a method of manufacturing a single-electron transistor device (). The method includes forming a thinned region () in a silicon substrate (), the thinned region () offset by a non-selected region (). The method also includes forming at least one quantum island () from the thinned region () by subjecting the thinned region () to an annealing process. The non-selected region () is aligned with the quantum island () and tunnel junctions () are formed between the quantum island () and the non-selected region (). The present invention also includes a single-electron device (), and a method of manufacturing an integrated circuit () that includes a single-electron device ().

A method for improving the thickness uniformity of a silicon-on-insulator (SOI) film on a semiconductor wafer. The preferred embodiments disclose using a selective epitaxial growth (SEG), sacrificial oxidation and an oxide removal process for improving SOI thickness uniformity. The SEG process is a leveling process that grows a materially identical layer of epitaxial silicon over the SOI layer, thus thickening the SOI layer and increasing its thickness uniformity. The sacrificial oxidation process oxidizes a portion of the newly thickened SOI layer, converting it into an oxide. An oxide removal process, commonly an etch process, removes the oxide produced by sacrificial oxidation while maintaining the thickness uniformity achieved by SEG leveling.

Method for improving silicon-on-insulator (SOI) film uniformity on a semiconductor wafer

A semiconductor processing tool evaluation and design method which replaces tool specifications with a requirements region plus associated evaluation functions for iterative feedback tool design.

Equipment evaluation and design

A system and process for analyzing the plasma discharge for various frequency components that can be correlated to wafer, chamber or equipment conditions. This system and process monitors (step 210), by using optical or electrical signals from the plasma, the low frequency plasma variations (step 220) generated during the wafer manufacturing process. For example, in endpoint detection applications, the amplitude variations of the plasma glow at a selected audio frequency, chosen for sensitivity to the etched material, is used to generate the endpoint signal (step 230). This endpoint signal has a potential response time equal to one cycle of the selected frequency plus minimal filtering due to noise reduction. To extract the vital parameters from the plasma glow, DSPs for frequency analysis or simple frequency filtering methods can be used.

Plasma etching with fast endpoint detector

A virtual sensor based monitoring and fault detection/classification system (10) for semiconductor processing equipment (12) is provided. A plurality of equipment sensors (14) are each operable to measure a process condition and provide a signal representing the measured process condition. A plurality of filtering process units (16) are each operable to receive at least one signal from the plurality of equipment sensors (14) and to reduce data represented by the at least one signal and provide filtered data. A plurality of virtual sensors (24) are each operable to receive the filtered data. The plurality of virtual sensors (24) model states of the processing equipment (12) and a work piece in the processing equipment (12). Each virtual sensor is operable to provide an output signal representing an estimated value for the modeled state. A rule based logic system (26) is operable to receive and process the signals provided by the plurality of equipment sensors (14) and the output signals provided by the virtual sensors (24) to monitor processing equipment (12) or to detect and classify faults within the processing equipment (12).

Virtual sensor based monitoring and fault detection/classification

An etching apparatus (10) includes a process chamber (12) partially surrounded by an upper electrode (14) and a lower electrode (16). A semiconductor material (18) lies within the process chamber (12) and in contact with the lower electrode (16). The lower electrode (16) is connected to a first power supply (22) operating at a substantially high frequency and is also connected to a second power supply (24) operating at a relatively low frequency. The lower frequency of the second power supply (24) provides a degree of anisotropic control to the trench etching process performed on the semiconductor material (18). The added anisotropic control allows for the elimination of sidewall deposition enhancing materials within a plasma chemistry introduced into the process chamber (12) by a gas distributor (20). Without the requirement of a sidewall deposition enhancing material during trench etching of the semiconductor material (18), buildup of residue due to sidewall deposition does not occur within process chamber (12).

Method and apparatus of etching a clean trench in a semiconductor

A method for testing for gas leaks in plasma reactors and gas lines introducing gas into the reactor, includes: measuring the intensity of the plasma reactor light emission; introducing known increments of a test gas into the reactor; measuring the intensity of the plasma reactor light emission after each introduction of an increment of test gas into the reactor; producing a curve resulting from the intensity readings vs increments of introduced gas; and performing a regression analysis on the curve to determine a value of gas at which the intensity is equal to zero, which value of gas is the amount of gas that has been leaked into the reactor.

Measurement of gas leaks into gas lines of a plasma reactor

Trace amounts of oxygen are removed from a plasma reactor by heating a filament during the times the reactor is not processing to cause the filament to react with the oxygen in the reactor, and forms an oxide of the filament material and the oxygen.

Oxygen scavenging in a plasma reactor

An apparatus and method for measuring the concentration profile of an active species across the surface of a semiconductor slice in a plasma reactor is disclosed that permits uniformity of etch and deposition across the surface of the semiconductor slice.

Method for measuring plasma properties in semiconductor processing

An apparatus and process for detecting aberrations in production process operations is provided. In one embodiment, operations of a plasma etch reactor (10) are monitored to detect aberrations in etching operations. A reference end-point trace (EPT) is defined (50), regions are defined in the reference EPT (52) and characteristics and tolerances for each region are defined (54). The etcher is run (56) and an actual EPT is obtained from the running of the etcher. The actual EPT is analyzed (58) by comparing characteristics of the regions of the actual EPT with characteristics of corresponding regions of the reference EPT. If the characteristics of the actual EPT exceed those of the reference EPT by predefined tolerances (62) a signal is generated (68). The system also checks for aberrations which are manifested by predefined EPT characteristics and signals when those are detected.

Growing community of inventors

Richardson, TX, United States of America

Gabriel George Barna