Cirrus Logic Inc.

Silicon Aquarius, Inc.

E Cirrus Logic, Inc.

G R Rao

Ronald T Taylor

Sudhir Sharma

Michael E Runas

Kirit B Patel

A memory 200 including an array 202 of addressable memory cells and a content addressable memory cell 207/300 for comparing a received select bit with a stored select bit and enabling access to addressed ones of the memory cells in response.

Memory architecture using content addressable memory, and systems and

A memory architecture 104 includes a plurality of arrays 200 of memory cells. Addressing circuitry 201 selects a cell of a selected one of arrays 201 for access while feature select circuitry 205 selects an access type to be performed to the selected cell. A first bus 207, 208, 209 exchanges a bit of data with the selected cell in response to the selection of a first access type. A second bus 207, 208, 209 exchanges a bit of data with the selected cell in response to the selection of a second access type.

Single chip controller-memory device including feature-selectable bank

A multivalue dynamic random access memory cell and method therefor are provided. Sense circuitry for sensing a most significant bit (MSB) and a least significant bit (LSB) of a binary data value are coupled to an unsegmented complementary bitline pair. The binary data is represented by a multilevel voltage stored on a storage element in the DRAM cell. A reference signal is provided to the sense circuitry, wherein the reference signal is independent of a precharge on the bitline pair. Cross-coupling elements offset the reference signal in response to the sensing of the MSB, whereby the voltage levels corresponding to the LSB are sensed. Following a read, the multilevel data value is restored on the storage element by a restore/write unit including a programmable voltage supply. The detected MSB/LSB pair are input to the restore/write unit which outputs the corresponding voltage level to the DRAM cell. A write is effected using the same restore/write unit with the binary datum to be stored input to the restore/write unit.

Methods and circuits for single-memory dynamic cell multivalue data

A memory 201 comprising an array 302 of memory cells, an address decoder 303, 305 for accessing a selected one of the cells in response to at least one address bit, and a programmable array 311 for selectively presenting the at least one address bit to the address decoder 303, 305 in response to a control signal.

Memories with programmable address decoding and systems and methods

A memory 400 including a memory cell 501 disposed at the intersection of an addressable row and addressable column, memory cell 501 being accessible via a selected one of a pair of wordlines 503a, 503b associated with the row and a selected one of a pair of bitlines 502a, 502b associated with the column.

Low latency memories and systems using the same

Memory 400 is fabricated as a single integrated circuit chip and includes an array 402 of memory cells and circuitry 404/405/413 for accessing selected memory cells in array 402. At least one local ALU 414 is included for receiving data accessed from selected cells of array 402 and performing a selected operation thereon.

DRAM with integral SRAM and arithmetic-logic units

A memory 200 comprising a first memory bank 201a including an array 202a of memory cells and a circuitry 203a, 205a for addressing a location within array 202a. Memory 200 further includes a second memory bank 201b including an array 202b of memory cells and circuitry 203b, 205b for addressing location within array 202b. Circuitry 203, 206, 207 is included for selectively pipelining a plurality of serially received words of address bits to the banks 201 during precharge of the banks.

Memory banks with pipelined addressing and priority acknowledging and

A memory includes a bitline comprised of 2 half-bitlines with at least one cell coupled to each of the half-bitlines. A sense amplifier for detecting a voltage difference is coupled between the half-bitlines. A control signal controls the current through the sense amplifier. A method is provided for sensing data by precharging a pair of half-bitlines, activating a storage cell coupled to one half-bitline and reference cell coupled to its complement. A sense amplifier senses the voltage difference between the half-bitlines by initiating current flow through the sense amplifier during an intitial period and increasing the current flow during a subsequent period.

Memories, systems, and methods using precision sense amplifiers

A dynamic random access memory (DRAM) includes priority access control circuitry, where the DRAM has a first precharge mode and a priority precharge mode. In the first precharge mode, the array is precharged during an external row address strobe (RAS) and accessed during an active state of the external RAS. In the priority precharge mode, the array is precharged during a precharge state of an internal RAS initiated by a priority signal received during any one of the precharge and active states of the external RAS, where the priority access control circuitry returns to the first mode on a subsequent precharge state of the external RAS.

Dynamic random access memory with a normal precharge mode and a priority

An amplifier 300 includes a differential pair of transistors 307a, 307b. A third transistor 306 controls current through transistors 307a, 307b of the differential pair in response to a stepped control signal.

Precision sense amplifiers and memories, systems and methods using the

A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Digital step generators and circuits, systems and methods using the same

A memory cell and structure are implemented to provide a memory system having the advantages of both static and dynamic memories. A dynamic memory cell is implemented using a capacitor to store charge associated with a data value stored in the cell. The storage capacitor is accessible through multiple switches, and each of the switches is coupled to an independent bitline. Because independent bitlines are implemented, one bitline may sense the data value stored within the memory cell, while a second bitline is pre-charged, or refreshed, for a next memory operation to be performed. Thus, as soon as data is provided to the first bitline, any memory cells sharing the second bitline are ready to be sensed and restored even though they are all in the same data memory array. Such sequential operation is not possible with prior art DRAM memory cells because they require a refresh period in which to pre-charge bitlines accessing the same memory location. By providing the ability to access the same memory cell during a next subsequent timing cycle, a DRAM cell having a very low latency is implemented.

Low latency DRAM cell and method therefor

A memory 400 comprises a plurality of banks 401 and global access control circuitry 406. Each of the plurality of banks includes first and second arrays 506, 402 of memory cells, first accessing circuitry 413, 507 for selectively accessing cells in the first array in response to address bits, and second accessing circuitry 404, 413 for selectively accessing cells in the second array in response to address bits. Storage circuitry 502 within each bank 401 stores previously received address bits. Circuitry for comparing 503 within each bank compares received address bits with stored address bits in storage circuitry 503, with first accessing circuitry 413, 507 accessing cells in first array 506 addressed by the stored address bits when stored address bits and received address bits match and second accessing circuitry 404, 413 accessing cells in second array 402 addressed by the received address bits when the stored address bits and the received address bits differ. Global access control circuitry 406 enables comparison of the stored address and the received address in a selected one of the plurality of banks 401.

Methods and systems for maintaining data locality in a multiple memory

A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.

Memory system with multiplexed input-output port and systems and methods

A memory subsystem with multiple memory banks each having an array of memory cells includes address control circuitry for presenting address bits to the row and column decoders of the memory banks and switching the row and column addresses presented to the different banks. Address control circuitry may be a translation look ahead buffer or may include an address translator, a row address buffer, and a column address buffer. The memory subsystem may also include input/output circuitry for inputting address bits in response to row address strobe and column address strobe signals. Input/output circuitry may allow both serial and parallel access to the multiple memory banks. A method for accessing the memory subsystem includes addressing a row in the array of a first memory bank using a first set of address bits, addressing a column in the array of the first memory bank using a second set of address bits, accessing a cell at the intersection of the selected row and selected column in the first memory bank, addressing a row in the array of a second memory bank using the second set of address bits, addressing a column in the array of the second memory bank using the first set of address bits, accessing a cell at the intersection of the selected row and selected column in the second memory bank.

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Dallas, TX, United States of America

G R Rao