Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Other

Renesas Electronics Corporation

Fumitoshi Yamamoto

Tomohide Terashima

Yasunori Yamashita

Tetsuo Higuchi

Tetsuya Nitta

Akio Uenishi

Hiroshi Onoda

Shinichiro Yanagi

Atsushi Tominaga

Keiichi Furuya

Kimitoshi Sato

An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through the nepitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Semiconductor device

The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an ntype semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Semiconductor device, driver circuit and manufacturing method of semiconductor device

A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an ndiffusion layer, an nepitaxial layer, an n-type diffusion layer and an ndiffusion layer. The ndiffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The ndiffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Semiconductor device with surge protection circuit capable of preventing current leakage

A base of a low breakdown voltage npn bipolar transistor has p diffusion layers. A field insulating layer is formed on the p diffusion layer located between the p diffusion layer and an emitter, while the p diffusion layer encloses the surface of the emitter and has a window part immediately under the emitter. Thus, a semiconductor device and a method of fabricating the same capable of suppressing dispersion of a current amplification factor h in a wafer plane of the low breakdown voltage transistor and fabricating the low breakdown voltage transistor and a high breakdown voltage transistor through simple steps are obtained.

Semiconductor device having low and high breakdown voltage transistors

A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P&plus; diffusion layer for dividing the epitaxial layer into an N&minus; epi layer, which constitutes a device formation region, and an N&minus; epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N&minus; epi layer (invalid area) to the P&plus; diffusion layer. Since the potential of the N&minus; epi layer (invalid area) can be made equal to that of the P&plus; diffusion layer, it is possible to prevent the electron supply from the P&plus; diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.

Semiconductor device having a device formation region protected from a counterelectromotive force

A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

The method for manufacturing a semiconductor device includes the steps of: removing an oxide film in a region including a fuse region at the formation of an opening for the formation of a vertical interconnection in an oxide film serving as an upper insulating layer; and forming the vertical interconnection for electrically connecting interconnection layers below and above the oxide film and the interconnection layer placed on an upper side of the oxide film as one upper conductive layer at the same time.

Method of manufacturing a semiconductor device including a fuse

A gate electrode layer is formed opposite to a p type backgate region posed between an n type source region and an n type epitaxial region, with a gate insulating layer interposed therebetween. A sidewall insulating layer is formed to cover a sidewall of the gate electrode layer. A p type backgate region has a relatively shallow p type diffusion region and a relatively deep p type diffusion region. The relatively deep p type diffusion region has a portion overlapping the relatively shallow p type diffusion region, and has its end portion at the substrate surface located directly beneath the sidewall insulating layer. Accordingly, a semiconductor device and a manufacturing method thereof that allow easy control of the threshold voltage of a DMOS transistor and facilitate realization of a rapidly operating bipolar transistor are attained.

Semiconductor device with DMOS and bi-polar transistors

An n epitaxial layer serving as a collector region is formed on a p-type silicon substrate. A p diffusion layer serving as a base region is formed on the n epitaxial layer. An n diffusion layer and an n diffusion layer defining an emitter region are formed on the p diffusion layer. A p diffusion layer serving as a base contact region for attaining contact with the p diffusion layer is formed with a prescribed interval between the same and the emitter region. Thus obtained is a semiconductor device comprising a transistor suppressing dispersion of a current amplification factor.

Semiconductor device comprising transistor

The present invention aims to provide a semiconductor device in which a satisfactory breakdown voltage can be obtained without increasing its chip size, and a method of manufacturing the same. A first electrode layer and a second electrode layer are formed. An inorganic type silicon oxide film is formed so as to cover first and second electrodes. An organic type silicon oxide film is formed on a surface of inorganic type silicon oxide film above a portion of a surface of first electrode layer. At a region of inorganic type silicon oxide film where organic type silicon oxide film is not formed, a through hole is formed, exposing a portion of a surface of second electrode layer. An interconnection layer is formed so as to be in contact with second electrode layer via through hole and opposing first electrode layer with inorganic and organic type silicon oxide films therebetween.

Semiconductor device and method of manufacturing the same

A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

Semiconductor device containing a diode

In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

CMOS semiconductor device

On a p.sup.+ diffused region which is to be a lower electrode of a capacitor, a silicon nitride film which is a capacitor insulating layer is formed. An upper electrode is formed on this silicon nitride film. The upper electrode has a non-doped polycrystalline silicon film and a silicide layer. Non-doped polycrystalline silicon film is formed in contact with silicon nitride film. Silicide layer is formed on a surface of non-doped polycrystalline silicon film. Thus, a capacitor structure is obtained in which a larger capacitance and a higher breakdown voltage can be assured, so that it would not operate inaccurately even when it is integrated to a higher degree.

Method of manufacturing a semiconductor device comprising a capacitor

An n-type epitaxial layer is formed on a main surface of a p-type silicon substrate. An n-type buried diffusion layer is formed extending in both the p-type silicon substrate and the n-type epitaxial layer. An n-type diffusion layer is formed in the surface of the n-type epitaxial layer, which is disposed above the n-type buried diffusion layer. A p-type diffusion layer is formed so as to surround side ends of the n-type diffusion layer. A p-type buried diffusion layer is formed so as to have a bottom face within the n-type buried diffusion layer and have side ends thereof inside side ends of the p-type diffusion layer. A collector region of a vertical pnp bipolar transistor consists of the p-type buried diffusion layer and the p-type diffusion layer. A p-type diffusion layer, which serves as an emitter region of the pnp bipolar transistor, is formed in the surface of the n-type diffusion layer. Thus, a semiconductor device having a vertical pnp bipolar transistor can be obtained which is capable of reducing its manufacturing cost and improving its reliability.

Growing community of inventors

Hyogo, Japan

Fumitoshi Yamamoto