Sandisk Corporation

Sandisk Technologies Inc.

Kabushiki Kaisha Toshiba

Fumitoshi Ito

Shinji Sato

Yingda Dong

Masaaki Higashitani

Man Lung Mui

Jayavel Pachamuthu

Tuan Duc Pham

Ken Oowada

Seungpil Lee

Teruhiko Kamei

Yosuke Kato

Cheng-Chung Chu

Takayuki Tsukamoto

Hiroshi Kanno

Takamasa Okawa

Youichi Minemura

Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

Offset backside contact via structures for a three-dimensional memory device

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.

Inter-plane offset in backside contact via structures for a three-dimensional memory device

According to one embodiment, a memory includes memory cells between first conductive lines and second conductive lines. A control circuit is configured to apply a first potential to a first end of a selected first conductive line connected to the selected memory cell among the first conductive lines and first ends of unselected second conductive lines not connected to the selected memory cell among the second conductive lines, apply a second potential larger than the first potential to a first end of a selected second conductive line connected to the selected memory cell among the second conductive lines, apply third potentials smaller than the second potential to first ends of unselected first conductive lines not connected to the selected memory cell among the first conductive lines respectively, and change values of the third potentials based on an address of the selected first conductive line.

Resistance change memory

Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during verify of an intermediate state (e.g., a lower page, middle page). The intermediate state is a state that exists during a program operation, but is not one of the final states. A lower back bias or no back bias is applied during verify of a final state (e.g., an upper page). Thus, a different back bias may be used when verifying an intermediate state than the back bias used when verifying a final state. Using the back bias makes it easier to verify a low V, such as a negative V. Also, using the back bias is effective at dealing with sense amplifier headroom issues.

Back bias during program verify of non-volatile storage

Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

Bit line current trip point modulation for reading nonvolatile storage elements

Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.

Fabricating and operating a memory array having a multi-level cell region and a single-level cell region

A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted ions below the end word lines increases a channel capacitance of the substrate under the end word lines. Due to the increased capacitance, boosting of a channel in the substrate below the end word lines is reduced, thereby reducing the occurrence of gate induced drain leakage (GIDL) and band-to-band tunneling (BTBT) and, consequently, program disturb. A shallow ion implantation may also be made to set a threshold voltage of storage elements of the NAND string.

Providing local boosting control implant for non-volatile memory

A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors.

Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects

Non-volatile memory with local boosting control implant

Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of the set to provide more consistent soft programming rates and threshold voltages. A first soft programming pulse can be applied to a first group of cells of the set while inhibiting soft programming of a second group of cells. A second soft programming pulse can then be applied to the second group of cells while inhibiting soft programming of the first group of cells. A small positive voltage of lower magnitude than the soft programming pulses can be applied to the group of cells to be inhibited. The size of the small positive voltage can be chosen so that each memory cell of the set will experience similar capacitive coupling effects from neighboring transistors when it is undergoing soft programming.

Growing community of inventors

Yokohama, Japan

Fumitoshi Ito