Elpida Memory, Inc.

Nec Corporation

Fumiki Aiso

Toshiyuki Hirota

Hirohito Watanabe

Masanobu Zenke

Shuji Fujiwara

Hiroyuki Fujimoto

Yuki Koga

Yasuhiko Ueda

Kyoko Miyata

Norishiro Komatsu

A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs.

Method of forming semiconductor device including trench gate structure

A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.

Semiconductor device having an elevated source/drain structure of varying cross-section

In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of the trench and a surface of the semiconductor substrate. A conductive film is formed to fill the trench whose surface is covered with the an insulating film. Source/drain regions are formed on both sides of the trench.

Semiconductor device and method of manufacturing the same

A semiconductor device provided with a semiconductor silicon substrate and gate wiring provided on the semiconductor silicon substrate via a gate oxide film, where the gate wiring has a gate electrode, a gate wiring upper structure provided in contact with the gate electrode, and a side wall spacer, the side wall spacer is comprised of one kind or two or more kinds of inorganic compound insulating layers, and at least one kind of the inorganic compound insulating layer is comprised of silicon oxynitride with a nitrogen content ranging from 30 to 70%.

A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon by allowing the crystal nuclei to grow in the solid phase.

Semiconductor device and method for producing the same

A silicon layer containing microcrystal is formed on a semiconductor substrate 10 having an amorphous silicon layer formed on the surface thereof (t and t ). Continuously, HSGs (hemispherical grains) are formed, in the same furnace, on the silicon layer using microcrystal on the silicon layer as a nucleus (t and t ). Further, a source gas containing impurities is introduced into the furnace to diffuse impurities into the HSGs (t and t ), wherein a lower electrode is formed. Also, during the processes from t through t , the partial pressure of water and oxygen in the furnace is set to 1&times;10 Torr or less. Furthermore, during the processes from t through t , the temperature in the furnace is set to 550 through 600&deg; C.

Method for producing capacitor elements, and capacitor element

In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the 'crystal nucleation' process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.

Process for forming a capacitor incorporated in a semiconductor device

In a silicon conductor doped with an impurity of 100 nm or less thick, a method is provided for manufacturing a silicon thin film conductive element which can prevent the increase of resistance with a low impurity concentration. The method includes the step in which, after the formation of an impurity-containing amorphous silicon film, a crystallization is performed without removing the film from a film forming device by performing a heat treatment while flowing a gas containing the impurity.

Method for manufacturing silicon thin film conductive element

In a capacitor incorporated in a semiconductor device, a capacitor lower plate is formed of a first amorphous silicon film on an interlayer insulator film and a second amorphous silicon film stacked on the first amorphous silicon film. A crystallization preventing film is formed between the first and second amorphous silicon films, or alternatively, the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. A stacked structure formed of the first and second amorphous silicon films is patterned into a capacitor lower plate having a top surface and a side surface, and hemispherical grains are formed on not only the top surface but also the side surface of the patterned stacked structure. In this process, crystalline growth from the interlayer insulator film is prevented by the crystallization preventing film or by the fact that the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. Thus, concaves and convexes in the form of hemispherical grains are uniformly formed on not only the top surface but also the side surface of the patterned stacked structure, so that a remarkably increased capacitance can be obtained.

Capacitor incorporated in semiconductor device having a lower electrode

At first, a silicon oxide layer is selectively formed on the surface of a semiconductor substrate. Next, a first amorphous silicon film doped with phosphorous in the concentration of about 1.times.10.sup.20 (atoms/cm.sup.3) and a non-doped second amorphous silicon film are deposited in sequential order. By this, an amorphous silicon layer for lower electrode constituted of the first and second amorphous silicon films is formed. Then, an HSG (unevenness) is formed on the surface of the amorphous silicon layer for lower electrode. Subsequently, the amorphous silicon layer for lower electrode is patterned to form a lower electrode of the stack type capacitive element. Thereafter, a capacitance insulation layer is formed on the upper surface and the side surface of the lower electrode. Then, over the entire surface, an upper electrode is deposited.

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Tokyo, Japan

Fumiki Aiso