Mitsubishi Denki Kabushiki Kaisha

Ryoden Semiconductor System Engineering Corporation

Renesas Technology Corp.

Fumihito Ohta

Tohru Koyama

Yasukazu Mukogawa

Toshikazu Tsutsui

Masaaki Furuta

Yohji Mashiko

A failure analysis method is provided that allows high-precision failure mode classification. Based on the result of a predetermined test using an LSI tester ( ), an original FBM ( ) is generated. The FBM ( ) is compressed with 8&times;8 bits per pixel to generate an FBM ( ). Based on the FBM ( ), an area where a failure bit exists in the FBM ( ) is determined. Then, by compressing a portion of the FBM ( ) which corresponds to the above area with 2&times;2 bits per pixel, FBMs ( ) are generated. Based on the FBMs ( ), failure bits are determined.

Failure analysis method that allows high-precision failure mode classification

An EWS for data analysis automatically performs automatic fatal failure extract processing on the basis of FBM information accumulated in a computer for a tester. In the automatic fatal failure extract processing, X-line repair judgment processing and Y-line repair judgment processing are continuously performed so that the X-line repair processing is performed in consideration of failures in a Y-line direction, and the Y-line repair judgment processing is performed in consideration of failures in an X-line direction. Further, the failures in the Y-line and X-line directions are taken into consideration from maximum ability decided by Y-line substitutability and X-line substitutability to zero. Thus provided is a failure analysis system capable of automatically investigating the cause for fatal failures.

Failure analysis system, fatal failure extraction method and recording

Data containing defect position coordinates obtained based on the result of physical inspection of foreign material, a defect or the like at the surface of a semiconductor wafer by a defect inspecting apparatus is stored. Also stored is data of physical coordinates obtained based on fail bit data from a tester. Data indicating an additional failure region is produced by an additional failure region estimating apparatus based on the fail bit data, and is stored. Collation produces data of corrected physical position coordinates by adding the stored data of limitation by failure mode to the stored data of physical position coordinates, and collates the data of corrected physical position coordinates with stored data of defect position coordinates. Accordingly, accuracy in collation is improved, and failure can be analyzed even if caused not by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure.

System for analyzing a failure in a semiconductor wafer by calculating

Data containing defect position coordinates obtained based on the result of physical inspection of a foreign material, a defect and the like at a surface of a semiconductor wafer by a defect inspecting apparatus is stored in storage means. Data of physical position coordinates obtained based on fail bit data from a tester is stored in storage means. Data indicating an additional failure region is produced by additional failure region estimating means based on the fail bit data, and is stored in storage means. Collating means produces data of corrected physical position coordinates by adding the data of limitation by failure mode stored in storage means to the data of physical position coordinates stored in storage means, and collates the data of corrected physical position coordinates with data of defect position coordinates stored in storage means. Accordingly, accuracy in collation is improved, and therefore, a failure can be analyzed even if the failure is not caused by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure. As a result, accuracy in estimation is improved.

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Tokyo, Japan

Fumihito Ohta