Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Other

Tower Semiconductor Ltd.

Fumihiko Noro

Nobuyoshi Takahashi

Seiki Ogura

Masataka Kusumi

Hiromasa Fujimoto

Shinji Odanaka

Masatoshi Arai

Akihiro Kamada

Koji Yoshida

Kenji Sato

Takahiko Hashidzume

Satoshi Iwamoto

Yakov Roizin

Keita Takahashi

Yoshinori Odake

Efraim Aloni

Micha Gutman

Menachem Vofsy

Avi Ben-Gigi

Masanori Tagami

Hiroaki Kuriyama

First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.

Method for fabricating semiconductor device

A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.

Method of forming a semiconductor device having a trapping film for charge accumulation

A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

Semiconductor device and method for fabricating the same

A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.

Semiconductor device having diffusion layers as bit lines and method for manufacturing the same

Semiconductor device

A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.

Semiconductor memory device and method for fabricating the same

A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.

Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays

A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.

Method of fabricating nonvolatile semiconductor memory device

A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor. A silicide layer is formed on the gate electrodes of the memory transistors, the gate electrode of the logic transistor and portions of the top faces, exposed from the sidewall insulating film, of impurity diffusion layers working as source/drain regions of the logic transistor.

Semiconductor memory and method for fabricating the same

Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100&deg; C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.

Nonvolatile semiconductor memory device and method of manufacturing the same

A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Nonvolatile semiconductor memory device and method for fabricating the same

A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.

The invention provides a floating gate semiconductor storage device equipped with an erase gate electrode that includes first and second diffusion layers, an isolation insulating film, a gate insulating film, a floating gate electrode, a control gate electrode, a capacitor dielectric film, an erase gate electrode and a tunneling insulating film. In manufacturing the semiconductor storage device, after forming the first and second diffusion layers in a semiconductor substrate, an insulating film for isolation is deposited on the semiconductor substrate. The insulating film for isolation is simultaneously or individually patterned into an isolation insulating film and first and second lower contact holes respectively reaching the first and second diffusion layers. The semiconductor device includes first and second contact members filled in the first and second lower contact holes to be in contact with the first and second diffusion layers. Therefore, in first and second upper contact holes formed in an interlayer insulating film disposed above the contact members so as to respectively reach the first and second contact members, the aspect ratio can be reduced.

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Toyama, Japan

Fumihiko Noro