Macronix International Co., Ltd.

Ful-Long Ni

Chin-Hsi Lin

Chung-Kuang Chen

Chun-Hsiung Hung

Chun-Jung Lin

Mam-Tsung Wang

Chin-Yi Huang

Chun-Yi Yang

Yi-Te Shih

Chung Kuang Chen

Nien-Chao Yang

Ching-Fang Yen

Chien-Sing Lee

Shi-Charng Ai

Jing-Wen Chen

Chang-Ju Chen

Chun-Li Chen

Meng-Chu Huang

A memory structure that improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus, each of the memory units of the memory structure is sensed correctly with its own appropriate set of reference currents, and the improvement of sensing accuracy is therefore achieved.

Memory structure, programming method and reading method therefor, and memory control circuit thereof

One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile memory, so that one of multiple clock signals is selected or the appropriate clock signal is generated to apply an appropriate threshold voltage window sensitivity.

Method and apparatus to control sensing time for nonvolatile memory

The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved.

A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory unit into a plurality of small memory groups; next, defining a threshold voltage distribution region for each small memory group; then, defining a plurality of program verify threshold voltages and a plurality of reference detecting values for each small memory group according to the threshold voltage distribution region of each small memory group; and after that, using these small memory groups to store data.

Method for memory data storage by partition into narrower threshold voltage distribution regions

The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

High density mask ROM having flat-type bank select

A compact integrated circuit with memory arrays, shared select transistors and distributed drivers of XDEC is disclosed. The shared select transistors are used to access two adjacent memory cell areas so that the overhead resulting from the conventional select areas can be reduced. The drivers of XDEC are distributed to both sides of the memory arrays to drive the memory cell areas so that conventional transfer areas can be reduced.

Compact integrated circuit with memory array

A MROM memory cell structure for storing multi level bit information is disclosed. First of all, a substrate is provided. The substrate has first and second trenches therein, wherein the first trench is deeper than second trench. A conformnal dielectric layer formed on sidewall and bottom of the first and second trenches. A conductive layer filled in the first and second trenches and on the substrate. A first doped region is formed under the first trench. A second doped region is formed under the second trench. A third doped region is formed in surface of the substrate and between the first and second trenches.

MROM memory cell structure for storing multi level bit information

A method of erasing a non-volatile memory. The non-volatile memory is positioned on a substrate of a semiconductor wafer and has a memory array region. The memory array region has memory cells, word lines and a substrate line electrically connected to the substrate of each memory cell in the memory array region. The erasing method is to control a potential difference between a word line not to be erased and the substrate to within a specific range, then supply a predetermined first potential to a word line to be erased, thereafter float the word line not to be erased, and finally supply the substrate line with a predetermined second potential. The potential difference between the first and the second potential drive the charges stored in the floating gate of the memory cell electrically connected to the word line to be erased to move into the channel through the tunneling oxide layer to complete the erasing. The charges stored in the floating gate of the memory cell electrically connected to the word line not to be erased will be affected by factors such as an initial potential supplied to the word line not to be erased, the floated word line not to be erased, a change of the substrate potential, and a voltage coupling effect between the substrate and the word line not to be erased. So, the potential difference between the word line not to be erased and the substrate can be controlled to a specific range, and the memory cell not to be erased is not affected.

Method of erasing a non-volatile memory

A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.

Method of fabricating mask read only memory

An electronically programmable semiconductor memory device that is able to provide stepped wordline voltages is disclosed. During programming of multi-level threshold voltages into memory cells within the electronically programmable semiconductor memory device, the stepped wordline voltages are used. The stepping through the wordline voltages is controlled by source-side voltage monitoring of the memory cells during programming. Threshold voltages of the memory cells are able to be programmed to three or more distinct voltage levels.

Electrically programmable semiconductor device with multi-level wordline voltages for programming multi-level threshold voltages

A method and apparatus for programming a non-volatile memory cell wherein the rate of current flowing through the cell is controlled via a current limiter coupled to the source node of the memory cell. The rate of current through the current limiter controls the programming current rate through the memory cell. The current limiter is controlled by an input which is dependant upon the setting of a current through an associated current mirror device. The current mirror current is controlled by a pre-defined input condition on a current source. The mirror current is used by a biasing circuit to generate a proportional input to the current limiter device. The current source thereby controls the current limiter rate. The current source can be formed from the same process as the memory cells and its output will thereby vary with the conductivity of the formed devices. This variation in the current source output, and hence the current limiter current, can be used to compensate for the comparable conductivity variations in the memory cells. The programming current rate can thereby be controlled, and can additionally be controlled according to process variations in the memory cell devices.

Method and device for programming a non-volatile memory cell by

The present invention provides a method and an apparatus for programming a selected call within a virtual ground EPROM array cell without disturbing adjacent array cells. The electrical disturbance of data stored in adjacent cells is limited in a number of ways: (1) a column connection circuit is provided for selectively coupling together adjacent pairs of even-odd or odd-even column lines so that source and drain terminals of adjacent memory cells are electrically coupled together, thereby preventing the data stored within the adjacent cells from being disturbed; (2) a current limiter circuit is provided for lowering a potential on a terminal of the selected cell at a controlled rate during programming so that voltages on terminals of the selected cell do not disturb data stored on adjacent memory cells; (3) the order in which programming signals are applied to terminals of the selected cell are controlled in such a way as to reduce the disturbance of data on adjacent cells; and (4) high wordline and data line voltages are applied to the selected cell in two steps, first to an intermediate voltage, and then to a high voltage. This reduces the disturbance to adjacent cells and improves programming.

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Hsinchu, Taiwan

Ful-Long Ni