Unisantis Electronics Singapore Pte. Ltd.

Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Unisantis Electronics (japan) Ltd.

Tokyo Shibaura Electric Co., Ltd.

Tohoku University

Toshiba Microelectronics Corporation

Unisantis Electronics

Unisantis Electronics Signapore Pte. Ltd.

Fujio Masuoka

Hiroki Nakamura

Nozomu Harada

Shintaro Arai

Masaki Momodomi

Tomohiko Kudo

Masamichi Asano

Koji Sakui

Riichiro Shirota

Yasuo Itoh

Shigeyoshi Watanabe

Tomoharu Tanaka

Yoshihisa Iwata

Ryouhei Kirisawa

Takehiro Hasegawa

Kazunori Ohuchi

Navab Singh

Shoji Ariizumi

Tetsuo Endoh

Fumio Horiguchi

Yisuo Li

Zhixian Chen

Ryozo Nakayama

Kavitha Devi Buddharaju

Kiyofumi Ochii

Mitsugi Ogura

Hiroshi Iwahashi

Tsuneaki Fuse

Taira Iwase

Satoshi Inoue

Nansheng Shen

Seiichi Aritome

Akihiro Nitayama

Xiang Li

Xinpeng Wang

Masahiko Chiba

Aashit Ramachandra Kamath

Takashi Mori

Yukihito Oowaki

Kenji Natori

Hisakazu Iizuka

Vladimir Bliznetsov

King-Jien Chui

Yu Jiang

Yoshiaki Kikuchi

Hiroshi Yasuda

Katsuhiko Hieda

Ryu Ogiwara

Shinichiro Shiratake

Toshiki Seshita

Makoto Segawa

Keon Jae Lee

Hiroshi Takato

Patrick Guo-Qiang Lo

Yasushi Fukatsu

Koichi Toita

Tetsuo Endo

Shioji Ariizumi

Syoji Ariizumi

R Ramana Murthy

Shen Nansheng

Rukmani Devi Sayanthan

Teng Soong Phua

Yoshiyuki Tanaka

Takeshi Hamamoto

Hiroshi Nakamura

Kenji Numata

Kazumasa Sunouchi

Hideko Odaira

Zheng Tao

Kaoru Nakagawa

Masashi Wada

Kei Kurosawa

Youichi Suzuki

Takeo Kondo

Masako Ohta

Min Soo Kim

Phillipe Matagne

In formation of an SRAM cell, a band-shaped contact hole Cis formed that does not overlap, in plan view. N+ layers, andformed on and at outer peripheries of the top portions of Si pillars, and, that partly overlaps W layersandon P+ layersandconnected to the top portions of Si pillarsand, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layersandthrough the contact hole Cis formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.

Pillar-shaped semiconductor device and method for producing the same

A gate TiN layer of adjacent Si pillars among Si pillars contacts at entire channel length in a vertical direction. SiOlayers are formed, surrounding the Si pillars, and mask material layers on top thereof, and being spaced from each other. Then, a SiN layer is formed surrounding the SiOlayers. Then, the mask material layers and the SiOlayers are removed. Then, a Player and Nlayers which upper surfaces are lower than an upper surface position of the SiN layer are formed surrounding each top of the Si pillars by selective epitaxial crystal growth method.

Manufacturing method of pillar-shaped semiconductor device

In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.

Pillar-shaped semiconductor device and manufacturing method thereof

A bottom portion of a Ta pillar serving as a contact portion is connected to an Nlayer and a Player, and a gate HfOlayer is connected to side surfaces of Si pillars and a Ta pillar serving as a contact portion and an upper surface of a SiOlayer between the Si pillars and the Ta pillar serving as the contact portion. Gate TiN layers are provided on a side surface of the gate HfOlayer surrounding the Si pillars. Midpoints of the Si pillars and the Ta pillar serving as the contact portion are on one first line in plan view.

An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an Nregion and a Pregion of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiOlayer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

Pillar-shaped semiconductor device having connection material layer for anchoring wiring conductor layer and method for producing the same

A second band-like mask material layer having a first band-like mask material layer of a same planar shape on its top is formed on a mask material layer on a semiconductor layer. Then, fourth band-like mask material layers having third band-like mask material layers of same planar shape on their top are formed on both side surfaces of the first and second band-like mask material layers. Sixth band-like mask material layers having fifth band-like mask material layers of same planar shape on their top are formed on the outside thereof. Then, an orthogonal band-like mask material layer is formed on the first band-like mask material layer, in a direction orthogonal to a direction in which the first band-like mask material layer extends. Semiconductor pillars are formed on overlapping areas of this orthogonal band-like mask material layer and the second and sixth band-like mask material layers by etching the semiconductor layer. Then, a pillar-shaped semiconductor device is formed with these semiconductor pillars being channels.

Method for manufacturing three-dimensional semiconductor device

A band-shaped Si pillar having a mask material layer on the top portion thereof is formed on a P+ layer. SiGe layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the band-shaped Si pillar and the surfaces of N+ layers and the P+ layer. Si layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the SiGe layers and the surfaces of the N+ layers. The outer peripheries of the bottom portions of the Si layers are then removed using the mask material layers as a mask to form band-shaped Si pillars. The mask material layers and the SiGe layers are then removed. Si pillars separated in the Y direction are then formed in the band-shaped Si pillars.

Method for manufacturing pillar-shaped semiconductor device

A SiOlayer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfOlayeris disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfOlayer. Players are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.

Semiconductor device having semiconductor pillar with first impurity region formed lower part of the pillar and second impurity region formed upper part of the pillar

A SiOlayeris formed in the bottom portion of a Si pillarand on an i-layer substrate. Subsequently, a gate HfOlayeris formed so as to surround the side surface of the Si pillar, and a gate TiN layeris formed so as to surround the HfOlayer. Subsequently, Playersandcontaining an acceptor impurity at a high concentration and serving as a source and a drain are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate

Method for producing pillar-shaped semiconductor device

An SGT is formed that includes Si pillars. The SGT includes WSilayers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

Semiconductor device including SGT

An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

Method for producing a pillar-shaped semiconductor device

The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiOlayer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiOlayer on the SiOlayer such that the SiOlayer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiOlayer in plan view, and a step of forming a SiOlayer by etching the SiOlayer below the SiOlayer and the resist layer using the SiOlayer and the resist layer as masks.

A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.

Method for producing a semiconductor device having a fin-shaped semiconductor layer

A Si substrate is etched through a first mask material layer formed on the Si substrate and serving as a mask, to form a Si pillar on a Si substrate. Subsequently, a second mask material layer formed so as to surround the side surface of the Si pillar is used as a mask to form a Si-pillar base part surrounding the Si pillar. Subsequently, the first and second mask material layers are used as masks to form a SiOlayer so as to occupy the whole section of the Si-pillar base part and connect to the Si substrate positioned in a region around the Si-pillar base part. Recessed portions are formed in the upper and lower regions of the SiOlayer. Subsequently, on the SiOlayer, an SGT is formed so as to include a gate insulating HfOlayer surrounding the Si pillar, a gate conductor TiN layer, Nlayers serving as the source or drain within the Si pillar, and a Si pillar serving as the channel between the Nlayers.

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Tokyo, Japan

Fujio Masuoka