Macronix International Co., Ltd.

Other

Macronix Internatioal, Ltd.

Fuchia Shone

Tom D Yiu

Tien-Ler Lin

Ray L Wan

Ling-Wen Hsiao

Ray-Lin Wan

Ling Chen

Tzeng-Huei Shiau

Chin-Yi Huang

Yun Shen Chang

I-Long Lee

Yao-Wu Cheng

Yuan-Chang Liu

Nai Chen Peng

Chun-Hsiung Hung

Kuen-Long Chang

Han-Sung Chen

Chun Hsiung Hung

Han Sung Chen

Chia-Shing Chen

Weitong Chuang

Ting-Chung Hu

Kong-Mou Liou

Chung-Hsiung Hung

Tso-Ming Chang

Chang Y Chang

Katsunori Onishi

Kuo Tung Sung

Chih Mu Huang

Hun-Song Chen

A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

Technique for increasing endurance of integrated circuit memory

A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

Fast flash EPROM programming and pre-programming circuit design

The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical 'Exclusive Or' of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

Memory supporting multiple address protocols

A read-only memory device is provided which comprises an array of read-only memory cells arranged in rows and columns. An additional row or column of flat, single polysilicon floating gate memory cells is provided. A row or column decoder coupled to the array of read-only memory cells is responsive to addresses corresponding to rows or columns in the array for selecting addressed rows or columns. Control circuitry including a programmable store for identifying a defective row or column in the array to be replaced by the additional row or column, selects the additional row or column and replaces the defective row or column in response to an address corresponding to the defective row or column. In addition, circuitry is provided on the integrated circuit which allows access to the additional row or column of floating gate memory cells for programming the additional row or column. The additional row or column of floating gate memory cells is comprised of flat or single polysilicon floating gate cells having buried diffusion control gates. This structure is particularly applied to an array of mask ROM cells. Furthermore, the additional row or column of floating gate memory cells can be implemented in layout of mask ROM cells itself, and a very dense compact structure without requiring additional process steps to implement the redundant row or column.

Memory redundancy circuit using single polysilicon floating gate

A technique for storing multiple bits per cell in a read only memory device, provides for two kinds of code implants in the memory array. A shallow implant such as used in prior art mask ROMs is used for coding a first bit, and a deeper implant is used for coding a second bit in the memory cells. Furthermore, the cells are implemented in a semiconductor substrate so that the channels of the transistors in the mask ROM can be biased. The memory cells include as isolation layer formed in the semiconductor substrate, and a channel well formed in the isolation layer. The device includes resources to apply a first bias potential such as ground, to channel regions of memory cells in the array. When the first bias potential is applied through the channel regions, the memory cells have particular thresholds determined at least in part by the dope concentrations in the channel regions. The device also includes resources to apply a second bias potential to the channel regions of the memory cells. When the second bias potential is applied, a shift in the threshold voltages in the memory cells is induced. The shift in threshold voltage occurs because of the so called body effect, and will be greater in the memory cells which have the deep implants, than in the memory cells which do not have the deep implants. The device also includes wordlines and bitlines by which to read the data stored in the array.

Method of forming a multi-level memory array with channel bias algorithm

A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.

Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate

A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.

Interpoly dielectric process

A process is provided for fabricating an integrated circuit in which an oxynitride layer is selectively formed in a first active region without forming an oxynitride layer in a second active region peripheral to the first active region. In one embodiment, the memory cell is fabricated where an oxynitride layer is prevented from forming in a region peripheral to the memory array region. In an alternate embodiment, the memory cell is fabricated where an oxynitride layer formed in a region peripheral to the memory array region is selectively removed.

Nitridation process with peripheral region protection

A dual mode memory cell and integrated circuit is provided with a native mode and a ROM mode. ROM code implants are incorporated into a standard memory array. The implants are deep implants which do not have a large effect on the threshold of the cell under normal substrate bias conditions. However, as the substrate bias is increased, they have an increasing effect on the cell threshold. Thus, the cells in one embodiment are floating gate cells that can be read in a flash mode, in which the threshold of the cell is determined predominately by charge stored in the floating gate of the cell, and a read only mode during which a substrate bias is applied, the charge stored in the floating gates in the sector to be read are equalized, and the threshold of the cell is determined predominately by the ROM code implants. Thus, more than one bit per cell is stored in the device, where one bit is stored in a read only mode and another bit is stored in a programmable and erasable mode in each cell in at least one sector of the memory device.

Dual mode memory with embedded ROM

Floating gate memory device and method for terminating a program load

Method and system for soft programming algorithm

Flash memory erase with controlled band-to-band tunneling current

An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

Non-volatile memory cell and array architecture

Growing community of inventors

Hsinchu, Taiwan

Fuchia Shone