Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manufacturing Intl. (beijing) Corp.

Semiconductor Manufacturing Intl. (shanghai) Corp.

Fucheng Chen

Herb He Huang

Haiting Li

Yanghui Xiang

Xinxue Wang

Hongbo Zhao

Linbo Shi

Yao Liu

Xingcheng Jin

Dekui Qi

The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. The method includes: forming a water film on a bottom surface of a top wafer and a top surface of a bottom wafer; after the water film is formed, attaching the bottom surface of the top wafer to the top surface of the bottom wafer; disposing the attached top wafer and bottom wafer in a vacuum environment; and performing a thermal annealing process, so that the bottom surface of the top wafer is fusion-bonded to the top surface of the bottom wafer. The disclosed methods can reduce bubble voids existing between the bonded wafers.

Method for manufacturing semiconductor apparatus

A semiconductor device includes a device substrate having a dielectric layer and a metal wire in the dielectric layer, a first opening on the metal wire and having a bottom at a depth the same as an upper surface of the metal wire, a first insulation layer including a first color filter material on sidewalls of the first opening, a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening, and a second insulation layer including a second color filter material on sidewalls of the second opening. The first opening is for leading out the metal wire to a pad. The second opening is disposed along scribe lines. The semiconductor device simplifies the process of drawing out and isolating the pads and satisfies technical requirements of a back seal ring.

Method and apparatus for backside illumination sensor

The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal blocks made of a second metal material. The plurality of first metal blocks are used to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.

Bonding pad structure, bonding ring structure, and MEMS device packaging method

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The semiconductor device also includes a plurality of transistors on the second semiconductor substrate, a deep trench isolation having a bottom at a surface of the first semiconductor substrate in the second region, the deep trench isolation exposing a sidewall of the second semiconductor substrate and a sidewall of the buried insulating layer, and a dielectric capping layer filling the deep trench isolation and covering the plurality of transistors on the second semiconductor substrate.

Deep trench isolation for RF devices on SOI

A method for manufacturing a substrate may include processing a substrate material member to form a first remaining portion. The first remaining portion has a first cavity. A sidewall the first cavity is oriented at a first angle with respect to at least one of a horizontal plane and a bottom side of the first remaining portion. The method may further include providing a sacrificial material member in the first cavity. The method may further include processing the sacrificial material member when processing the first remaining portion to remove the sacrificial material member and to form a second remaining portion. The second remaining portion has a second cavity. A sidewall the second cavity is oriented at a second angle with respect to at least one of the horizontal plane and a bottom side of the second remaining portion. The second angle is smaller than the first angle.

Substrate, related device, and related manufacturing method

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

Method for forming deep trench isolation for RF devices on SOI

A method for manufacturing a semiconductor device may include providing a first dielectric layer and a first set of conductive pads on a first substrate. Each conductive pad of the first set of conductive pads may be positioned between portions of the first dielectric layer. The method may further include providing a first insulating material layer to cover the first dielectric layer and the first set of conductive pads. The method may further include removing portions of the first insulating material layer to form a first insulating layer. Openings of the first insulating layer may expose the first set of conductive pads.

Semiconductor device and related manufacturing method

A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

Growing community of inventors

Shanghai, China

Fucheng Chen