Globalfoundries Inc.

Fuad H Al-Amoody

Jinping Liu

Yiheng Xu

Rishikesh Krishnan

Bharat V Krishnan

Haifeng Sheng

Joseph K Kassim

The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.

Fin structures

Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

Protected trench isolation for fin-type field-effect transistors

One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.

Methods of forming spacers on FinFET devices

One illustrative method disclosed herein includes, among other things, forming first and second fins, forming a liner layer above at least a first upper surface of the first fin and a second upper surface of the second fin, and forming an ion-containing region in the first portion of the liner layer while not forming the ion-containing region in second portion of the liner layer. The method also includes performing a liner etching process so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned above the first fin, and performing at least one etching process to define a reduced-height second fin that is less than an initial first height of the first fin.

Growing community of inventors

Rexford, NY, United States of America

Fuad H Al-Amoody