Force Mos Technology Co., Ltd.

Nami Mos Co, Ltd

Other

Force-mos Technology Corporation

Feei Cherng Enterprise Co., Ltd.

Fu-Yuan Hsieh

Ming-Tao Chung

The present invention introduces new shielded gate trench (SGT) superjunction (SJ) MOSFETs having a first type multiple stepped epitaxial (MSE) structure in oxide charge balance (OCB) region and a second type MSE structure in SJ region for improved specific on-resistance Rsp and gate-to-drain charge Qgd. The two-type MSE structures can increase the average doping concentration in drift regions of the SGT SJ MOSFETS, as a result, lower Rsp and higher avalanche capability could be achieved without degrading breakdown voltage.

Superfunction MOSFETs having shielded gate trench structures

The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

Shielded gate trench MOSFETs with improved performance structures

Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein at least one termination trench surrounds outer periphery of gate trenches and does not surround the gate metal pad area. The shielded gate electrode inside each of the gate trenches is connected to a source metal through at least one shielded gate trench contact which is spaced apart from at least one gate metal runner with a distance larger than 100 um. A breakdown voltage enhancement region and an avalanche capability enhancement region in the device structures are also disclosed.

Shielded gate trench MOSFETs with improved trench terminations and shielded gate trench contacts

Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein the termination trenches surrounds outer periphery of gate trenches and do not surround said gate metal pad area; Inner edges of a first termination trench of the termination trenches adjacent to trench ends of the gate trenches have a plurality of wave shape portions in regions between two adjacent trench ends of the gate trenches while outer edges have a straight shape to reduce drain-source leakage current. Each of gate trenches on which has at least one shielded gate trench contact connected to a shielded gate electrode, and the shielded gate trench contact is spaced apart from any of multiple gate metal runners with a distance larger than 100 um.

The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage Vis significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

Super barrier rectifier with shielded gate electrode and multiple stepped epitaxial structure

An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

SiC trench MOSFET with low on-resistance and switching loss

A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Trench MOSFETs integrated with clamped diodes having trench field plate termination to avoid breakdown voltage degradation

A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

Shielded gate trench MOSFET with ESD diode manufactured using two poly-silicon layers process

A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

SiC super junction trench MOSFET

A SGT MOSFET having two stepped oxide (TSO) structure in gate trench is disclosed, wherein the TSO has thinner oxide thickness along upper sidewalls of the gate trench than along lower sidewalls of the gate trench. The BV can be enhanced as result of the electric filed reduction near channel region, on-resistance is thus reduced. The present invention further comprises a super junction region below the oxide charge balance region, making vertical electrical field more uniform, the BV is further enhanced and on-resistance is further reduced.

Shielded gate trench MOSFET having improved specific on-resistance structures

An integrated circuit comprising an SGT MOSFET and a short channel SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel for switching loss reduction. Only one additional mask is required for integration of the short channel SBR having thinner gate oxide than the SGT MOSFET. Moreover, in some preferred embodiment, an MSO structure is applied to the shielded gate structure to further reduce the on-resistance.

Shielded gate trench MOSFET integrated with super barrier rectifier having short channel

An integrated circuit comprising a surrounding gate transistor (SGT) MOSFET and a super barrier rectifier (SBR) is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel, therefore has lower forward voltage and reverse leakage current than conventional Schottky Barrier Rectifier. Moreover, in some preferred embodiment, a multiple stepped oxide (MSO) structure is applied to the shielded gate structure to further reduce the on-resistance.

Shielded gate trench MOSFET integrated with super barrier rectifier

A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of multiple trench MOSFETs connected together with multiple sawing trenched gates across a space between two trench MOSFETs having a width same as scribe line. Dummy cells formed between an edge trench and active area act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

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New Taipei, Taiwan

Fu-Yuan Hsieh