United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Fu-Shou Tsai

Kun-Ju Li

Yu-Ting Li

Po-Cheng Huang

Li-Chieh Hsu

Wen-Chin Lin

Yi-Liang Liu

Chun-Tsen Lu

Kuo-Chin Hung

Jen-Chieh Lin

Min-Chuan Tsai

Wei-Chuan Tsai

Chih-Hsun Lin

Yang-Ju Lu

Wu-Sian Sie

Yu-Lung Shih

Ji-Min Lin

Chien-Nan Lin

Chun-Liang Liu

Yi-Han Liao

Yong-Yi Lin

Ching-Yang Chuang

Yi-Wei Chen

Chih-Chien Liu

Chun-Yuan Wu

Chen-Yi Weng

Jing-Yin Jhang

Chau-Chung Hou

Rung-Yuan Lee

Wei-Xin Gao

Wei-Jen Wu

Hsin-Jung Liu

Chun-Han Chen

I-Ming Lai

Ang Chan

Jia-Feng Fang

Jhih-Yuan Chen

I-Lun Hung

Shih-Ming Lin

Lan-Ping Chang

Zong-Sian Wu

A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Method for manufacturing semiconductor device

A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

Fabricating method of transistors without dishing occurred during CMP process

The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

Method of manufacturing a semiconductor device

A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Method for forming semiconductor integrated circuit structure

Semiconductor integrated circuit structure

A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

Planarization method

The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

Wafer polishing pad and using method thereof

A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

Conductive layout structure including high resistive layer

Semiconductor integrated circuit structure and method for forming the same

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

Method of planarizing substrate surface

A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

Method of fabricating a gate cap layer

A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

Method for forming semiconductor structure

A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

Conductive structure having an entrenched high resistive layer

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

Method for planarizing material layer

Growing community of inventors

Keelung, Taiwan

Fu-Shou Tsai