Taiwan Semiconductor Manufacturing Comp. Ltd.

Fu-Kai Yang

Mei-Yun Wang

Chen-Ming Lee

I-Wen Wu

Hsien-Cheng Wang

Po-Yu Huang

Chun-Han Chen

Chao-Hsun Wang

Shih-Wen Liu

Hsin-Ying Lin

Jia-Heng Wang

Shao-Ming Koh

Jr-Hung Li

Audrey Hsiao-Chiu Hsu

Kuo-Yi Chao

Chien-Yuan Chen

Yun Lee

Yen-Ming Chen

Wei-Yang Lee

Chung-Ting Ko

Sheng-Hsiung Wang

Bo-Cyuan Lu

Chen-Hung Tsai

Jui-Ping Lin

Ting Fang

Chia-Hsien Yao

Kai-Hsuan Lee

Peng Wang

Shih-Che Lin

Cheng-Yu Yang

Pang-Chi Wu

Hsiao-Chiu Hsu

Tze-Liang Lee

Yung-Cheng Lu

Tai-Chun Huang

Shu-Yuan Ku

Yen-Ting Chen

Wei-Yuan Lu

Ming-Chang Wen

Guan-Ren Wang

Ting-Gang Chen

Chun-An Lin

Yi-Jyun Huang

Yi-Ting Fu

Kai-Di Tzeng

Pang-Sheng Chang

Chung-Hao Cai

Chi On Chui

Ping-Wei Wang

Shih-Hao Lin

Chang-Yun Chang

Chun-Wei Hsu

Ching-Feng Fu

Chia-Der Chang

Jui-Lin Chen

Li-Chieh Wu

Tzu-Hsiang Hsu

Shu-Huei Suen

Yi-Chun Lo

Shih-Hsien Huang

Chao-Yuan Chang

Liang-Yi Chen

Hung-Chang Hsu

Wang-Jung Hsueh

Shih-Chieh Wu

Guo-Chiang Chi

Chia-Ping Lo

Chun Po Chang

Tien-Chun Wang

Feng-Cheng Yang

Jyu-Horng Shieh

Chi-Cheng Hung

Da-Wen Lin

Sheng-Liang Pan

Yuan-Ching Peng

Chen-Yuan Kao

Jian-Hao Chen

Yu-Feng Yin

Feng-Yu Chang

Shao-Jyun Wu

Chia-Yang Hung

Jack Kuo-Ping Kuo

Tzu-Yang Ho

Chia-Sheng Chang

Jason Yao

Yen-Jun Huang

Chun-Po Chang

A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.

Contact profile optimization for IC device performance improvement

Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure is through the dielectric layer. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and the bottommost surface of the bridging contact structure is in direct contact with the topmost surface of the S/D contact structure.

Semiconductor structure with conductive_structure

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.

Semiconductor transistor structure with nanostructures and conductive structure and method for manufacturing the same

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

Silicide backside contact

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Isolation structure and a self-aligned capping layer formed thereon

A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Semiconductor device structure and method for forming the same

In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Semiconductor devices

A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and an S/D conductive plug formed over the protection layer. The S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same

Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Epitaxial source/drain structures for multigate devices and methods of fabricating thereof

An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Dielectric structures for semiconductor device structures

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Semiconductor device with backside spacer and methods of forming the same

A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Method of forming backside power rails

A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Silicide structures in transistors and methods of forming

A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Interconnect structures and methods of fabrication thereof

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Semiconductor device structure and methods of forming the same

Growing community of inventors

Hsinchu, Taiwan

Fu-Kai Yang