Taiwan Semiconductor Manufacturing Comp. Ltd.

Fu-Jen Li

Po-Yao Lin

Ming-Chih Yew

Kuo-Chuan Liu

Pei-Haw Tsao

Wen-Yi Lin

Shyue-Ter Leu

Heh-Chang Huang

Hsiu-Mei Yu

Chia-Jen Cheng

Shou-Wen Kuo

Cheng-Yi Huang

Shu-Jung Tseng

Yue-Lin Peng

Chih-Hao Lin

Hsien-Liang Meng

Chien-Kuo Chang

Pu-Sheng Lee

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

Semiconductor device package having warpage control

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer, wherein a first thickness of the conductive pillar is substantially equal to a sum of a second thickness of the second chip structure and a third thickness of the first conductive bump. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar.

Method for forming chip package structure

A semiconductor package includes an interposer, a die and a first encapsulant. The die is bonded to the interposer, the die has a protective layer thereon, wherein the protective layer and the interposer are disposed on opposite sides of the die, and the protective layer is not extended beyond an outer sidewall of the die. The first encapsulant is disposed aside the die and the protective layer.

Semiconductor packages

Semiconductor device package having warpage control and method of forming the same

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.

Semiconductor device package with warpage control structure

A semiconductor package includes an interposer, a die, a protective layer, a plurality of first electrical connectors and a first molding material. The die includes a first surface and a second surface opposite to the first surface, and the die is bonded to the interposer through the first surface. The protective layer is disposed on the second surface of the die. The first electrical connectors are disposed aside the die. The first molding material is disposed aside the die, the protection layer and the first electrical connectors.

Semiconductor packages and method of manufacturing the same

Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.

A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.

Methods for selectively forming identification mark on semiconductor wafer

A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

Packages with multi-thermal interface materials and methods of fabricating the same

Mini identification mark in die-less region of semiconductor wafer

Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

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Hsin-Chu, Taiwan

Fu-Jen Li