Taiwan Semiconductor Manufacturing Comp. Ltd.

Fu-Chiang Kuo

Shih-Chi Kuo

Tsung-Hsien Lee

Tao-Cheng Liu

Ying-Hsun Chen

Jen-Yuan Chang

Cheng-Wei Lo

Min-Hsiung Chen

Yu-Hsin Fang

Yu-Han Chen

A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Deep trench protection

A semiconductor structure comprises a semiconductor substrate, a first trench capacitor, and a second trench capacitor. The substrate has first trenches arranged in a first arrangement direction with each first trench extending in a first extension direction and second trenches arranged in a second arrangement direction with each second trench extending in a second extension direction. The first trench capacitor includes first capacitor segments disposed inside the first trenches. The second trench capacitor includes second capacitor segments disposed inside the second trenches. One first capacitor segment of the first capacitor segments has an extending length different from that of another first capacitor segment of the first capacitor segments, and one second capacitor segment of the second capacitor segments has an extending length different from that of another second capacitor segment of the second capacitor segments.

Package structure having trench capacitor

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. In one aspect, at least one active deep trench capacitor (DTC), the at least one active DTC including a plurality of conductive layers and an insulating layer disposed between adjacent conductive layers of the plurality of conductive layers. The semiconductor device includes a plurality of dummy DTCs disposed on opposing sides of the at least one active DTC, the plurality of dummy DTCs and the at least one active DTC arranged in a row. The semiconductor device includes a plurality of conductive structures connected to the plurality of conductive layers of the active DTC, the plurality of dummy DTCs insulated from the at least one active DTC.

Semiconductor device including dummy deep trench capacitors and a method of manufacturing thereof

A capacitance structure comprises a metal nitride layer, such as a titanium nitride (TiN) layer, a compositionally graded film formed on a surface of the metal nitride layer by thermal oxidation, and a dielectric layer disposed on the compositionally graded film. A method of manufacturing a capacitance structure includes forming a conductive layer, performing thermal oxidation of a surface of the conductive layer to produce a compositionally graded film on the conductive layer, and forming a dielectric layer on the compositionally graded film.

Capacitance structure

A method includes forming first-type deep trenches and second-type deep trenches in a substrate, in which the first-type deep trenches have a first lengthwise direction along a first direction and the second-type deep trenches have a second lengthwise direction along a second direction; forming a capacitor structure over the substrate and in the first-type deep trenches and the second-type deep trenches, in which the capacitor structure includes a first metallic electrode layer, a node dielectric layer over the first metallic electrode layer, and a second metallic electrode layer over the node dielectric layer; and forming a first metal via over the capacitor structure and in contact with the second metallic electrode layer of the capacitor structure, in which a length of the first metal via is greater than a width of the first metal via from a top view.

Deep trench capacitor structure and method for forming the same

A semiconductor structure includes a substrate containing first-type deep trenches and second-type deep trenches. The first-type deep trenches and the second-type deep trenches have lengthwise sidewalls that laterally extend along different directions. The semiconductor structure includes a capacitor structure, which includes a layer stack containing at least three metallic electrode layers interlaced with at least two node dielectric layers. Each layer within the layer stack includes a horizontally-extending portion that overlies a top surface of the substrate and vertically-extending portions that protrude downward into a respective one of the first-type deep trenches and second-type deep trenches. The different orientations of the lengthwise directions of the deep trenches reduces deformation of the semiconductor structure. Stress-relief structures may be formed in corner regions of the capacitor structure to provide structural reinforcement.

Deformation-resistant deep trench capacitor structure and methods of forming the same

A semiconductor die includes an array of first capacitor regions, each of the first capacitor regions including multiple first capacitor cell structures, wherein each first capacitor cell structure includes a plurality of first trench segments characterized by a first trench length, a first trench width, and a first trench spacing, and a first air gap width in a gap-filling material. The semiconductor die also includes a plurality of second capacitor regions interspersed in the array of first capacitor regions, each of the second capacitor region including multiple second capacitor cell structures, wherein each second capacitor cell structures includes a plurality of second trench segments characterized by a second trench length, a second trench width, a second trench spacing, and a second air gap width in the gap-filling material.

Deep trench capacitor array with reduced warpage

A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.

Semiconductor trench capacitor structure and manufacturing method thereof

A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

Deep trench capacitor including stress-relief voids and methods of forming the same

A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first passivation layer on the SiC layer, removing a portion of the first passivation layer to form a first opening, forming a second passivation layer on the first passivation layer, the second passivation layer including a first portion in the first opening, and forming a second opening by removing a part of the first portion of the second passivation layer. The forming the second opening exposes the top metal layer.

Growing community of inventors

Hsinchu, Taiwan

Fu-Chiang Kuo