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United States of America As Represented by the Secretary of the Air Force

USA As Represented by Secretary of the Navy

Fritz L Schuermeyer

Charles R Young

Michael Shur

Charles L Cerny

Edgar J Martinez

Marino J Martinez

Paul E Cook

This is a fabrication process for complementary III-V HFETs in which devices are built side-by-side in doped-areas, known as 'tubs', grown by molecular beam epitaxy on indium phosphide (InP) substrates, or other material systems such as materials grown on GaAs substrates. The layers grown are a semi-insulating buffer layer of InAlAs, a InGaAs channel, an InAlAs barrier layer and finally an InGaAs cap layer. All layers are lattice matched or pseudomorphic to the InP substrate. After mesa etching of areas around the transistor, a high temperature silicon nitride (Si.sub.3 N.sub.4) layer is deposited using chemical vapor deposition, and photoresist is deposited. Then n-well and p-well areas are formed in turn, with appropriate ion-implantation, stripping of the photoresist, and annealing to activate the dopants. Then the Si.sub.3 N.sub.4 is stripped and the samples thoroughly cleaned. Then, the refractory gate metal is sputtered, delineated with photoresist and reactive ion etch procedures. Areas for n-ohmic and p-ohmic contacts are formed, using with Si.sub.3 N.sub.4 and photoresist covering, ion implanting, and annealing. Finally the p- and n-ohmic contact metals are evaporated and alloyed. The typical n-ohmic metal system is Au/Ge/Ni while Au/Zn is used for the formation of the p-ohmic contacts. The integrated circuit is completed by depositing and patterning the interconnect metal.

Twin-tub complementary heterostructure field effect transistor fab

It is desirable to implement complementary field effect transistors in group III/group V compound semiconductors, especially on InP substrates. Outstanding n-channel performance has been demonstrated in InGaAs channel devices on InP substrates. Preliminary experiments indicate that GaAsSb channel devices will result in optimal p-heterostructure FETs (HFETs). This disclosure teaches a technique to fabricate both n- and p-channel devices on the same substrate, allowing the demonstration of (C-HFET) technology. The HFET structure contains a channel region and the barrier region. The channel region consists of two distinctive parts: the p-channel and the n-channel areas. The p-channel area consists of GaAsSb, lattice matched to the InP substrate. In n-channel FETs, and ohmic contacts are formed by first doping the contact areas with Si by ion implantation, annealing the structure and then depositing and annealing the ohmic metal. In the complementary FET p-channel FETs, BE ion implementation is used for formation of ohmic contacts.

Making staggered complementary heterostructure FET

The IGFET is formed on a GaAs wafer which is coated with a layer of Si.sub.3 N.sub.4 and a SiO.sub.2 layer. The SiO.sub.2 is etched away in transistor areas, and ion implanting provides channel doping. A gate of refractory metal such as Mo is deposited and delineated. The gate and the SiO.sub.2 act as masks for ion implantation of the source and drain. The refractory metal gate allows subsequent annealing at high temperatures to activate the ion implanted species.

Method of making self-aligned IGFET

GaAs digital electronics uses mainly depletion mode MESFET technology. In typical circuits, negative voltage logic input signals are required while the output voltage is positive. To connect gates, level shifters are needed to shift the positive voltage output signals such that they become suitable for the input to the next gate. A capacitor is used which performs the level shifting. As the charge leaks off the capacitor, the voltage level has to be readjusted periodically, leading to a 'dynamic' circuit. A method for self-biasing of the capacitor for readjustment of the voltage level is taught.

Dynamic MESFET logic with voltage level shift circuit

A technique to utilize GaAs insulated gate field effect transistors (IGFETs) with large surface state densities in digital integrated circuits including latches is described. In this technique, the threshold voltage is electrically set to obtain enhancement mode characteristics of the IGFETs. Due to changes in surface charge with time, these circuits will not function at very low frequencies, but are very useful at gigahertz frequencies.

Gallium arsenide MIS integrated circuits

The memory cell uses GaAs MESFET depletion mode devices, with a pair of cross coupled active transistors, a pair of load transistors, and a pair of access transistors. The level shifting required for Schottky Barriers is provided by capacitors in the cross coupling. A pair of initiation transistors are connected between the load and active transistors.

Dynamic random access memory cell using field effect devices

A nonvolatile memory cell is disclosed that has a buried n+ layer from which charge (electrons) is injected into the insulator of n-channel MNOS (Metal Nitride Oxide Semiconductor) type devices.

Nonvolatile punch through memory cell with buried n+ region in channel

A nonvolatile Charge Injection Device (NOVCID) of Metal-Nitride-Oxide-Semiconductor (MNOS) material is operated in a novel manner in combination with a flip-flop to provide a charge pumped volatile memory storage system that can be continuously nondestructively read and on command, by applying a high positive potential to the field plate of the NOVCID, the information stored in the volatile mode is transferred to the nonvolatile state. To recover the stored information an alternating current signal is applied to the field plate.

Quasi static, virtually nonvolatile random access memory cell

A dynamic, virtually nonvolatile random access memory (RAM) storage cell is provided by storing information in a Nonvolatile Charge Injection Device (NOVCID), first in volatile form, then by an electric signal transferring the stored intelligence into a nonvolatile form from which it may late be recovered. Since only on external command is the information transferred into the nonvolatile storage mode, the memory is described as a virtually nonvolatile RAM.

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Yellow Springs, OH, United States of America

Fritz L Schuermeyer