Stats Chippac Pte. Ltd.

Chippac, Inc.

Stat Chippac Ltd.

Frederick Rodriguez Dahilig

Zigmund Ramirez Camacho

Lionel Chien Hui Tay

Dioscoro A Merilo

Henry Descalzo Bathan

Sheila Marie L Alvarez

Antonio Bambalan Dimaano, Jr

Jairus Legaspi Pisigan

Hin Hwa Goh

Geun Sik Kim

Robinson Quiazon

Jae Soo Lee

Arnel Senosa Trasporto

Philip Lyndon Cablao

Sheila Alvarez

A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps

A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

In a wafer level chip scale package (WLCSP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLCSP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.

Semiconductor device and method of forming wafer level die integration

An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.

Integrated circuit package system with device cavity

A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.

Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers

A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.

Integrated circuit packaging system with high lead count and method of manufacture thereof

A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Semiconductor flip chip package having substantially non-collapsible spacer and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the substrate external layer; forming an insulation layer over the substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect; and connecting an integrated circuit and the horizontal conductive pathway.

Integrated circuit packaging system with interconnect and method of manufacture thereof

Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps

Wafer level die integration and method

A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.

Integrated circuit package system employing device stacking

A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.

Growing community of inventors

Singapore, Singapore

Frederick Rodriguez Dahilig