Texas Instruments Corporation

Other

Frederick G Wall

Bernhard H Andresen

Terence G Blake

William H Baker

Stephen C Kwan

Terence G W Blake

A voltage level shifter with testable cascode devices is disclosed. According to one embodiment, the level shifter includes multiple cascode devices and switches a first output driver according to the values of a data input and an enable input. Testability devices coupled to cascode devices of the level shifter detect a current in response to failure of the corresponding cascode device.

Voltage level shifter with testable cascode devices

A fail-safe Input/Output buffer bias circuit for digital CMOS chips provides protection for Input/Output buffers which have high voltages applied to the Input/output node and are subjected to power supply failure resulting in a collapsing supply voltage decaying to zero volts while said Input/output circuit has a high voltage remaining applied to its Input/output node. The Input/output buffer bias circuit is comprised of a sensing circuit and a bias generator circuit which acts to drive protection transistors in a manner which optimally minimizes the voltage impressed on input or output devices under all conditions which could persist in the event of V,supply voltage failure. Protection circuitry holds all three combinations of voltage stress, gate-to-source, gate-to-drain, and drain-to-source voltages, to acceptable levels.

Method of designing fail-safe CMOS I/O buffers whose external nodes accept voltages higher than the maximum gate oxide operating voltage

A test circuit (,) is provided to enable testing for faults in internal cascode transistors Q,and Q,, which form part of, for example, a level shifting circuit. Test circuit (,) is comprised of test transistors Q,and Q,connected to regulating transistors Q,and Q,. When Q,and Q,are functioning properly, no current flow through test circuit (,). If, however, either or both of Q,or Q,has a drain to source short, current flows through test circuit (,) thus providing an indication of the fault.

Testability circuit for cascode circuits used for high voltage interface

According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) having a gate oxide protected from voltage changes on an output (16). A second output driver (88) also has a gate oxide protected from voltage changes on the output (16). A level shifter (60) includes at least one cascode device (66, 68, 70, 72) and switches the first output driver (86) according to the values of a data input (12) and an enable input (14). A bias-generation circuit (300) generates a quasi-failsafe voltage that is approximately equal to a chip core voltage when a power supply (4) is supplying the chip core voltage and equal to a portion of the chip core voltage when the power supply (4) is not supplying the chip core voltage. The bias-generation circuit (300) is coupled to a first output cascode (80) coupled to the first output driver (86), to a second output cascode (84) coupled to the second output driver (88), or to the cascode device (66, 68, 70, 72) of the level shifter (60).

Output buffer having quasi-failsafe operation

According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) and a second output driver (88). A first output cascode (80) coupled to the first output driver (86) protects the gate oxide of the first output driver (86) from voltage changes on the output (16). A second output cascode (84) coupled to the second output driver (88) protects the gate oxide of the second output driver (88) from voltage changes on the output (16). A level shifter (60) includes multiple cascode devices (66, 68, 70, 72) and switches the first output driver according to the values of a data input (12) and an enable input (14). A first testability device (202, 204, 206, 208) coupled to a cascode device (66, 68, 70, 72) of the level shifter (60) generates a current in response to failure of the cascode device (66, 68, 70, 72).

Output buffer providing testability

A gate array base cell (100) performs logic and memory cell functions and comprises a first P-channel transistor (M1) for performing logic functions and having a first predetermined transconductance area and a second P-channel transistor (M5) for performing memory cell functions and having a second predetermined transconductance area. The second transconductance area is smaller than said first predetermined transconductance area. The gate array base cell (100) has programmable connections to first P-channel transistor (M1) and second P-channel transistor (M5) for selectively performing memory cell functions and logic functions. The gate array base cell (100) may be connected to operate as a memory cell with logic functions or separately as a memory cell or a logic gate array, such as a two-input NAND gate (128).

Gate array base cell with multiple P-channel transistors

Current sensing circuits especially adapted for use with either capacitive touch plate or mechanical switch keys. The circuits include a transistor whose base is connected to a constant voltage source and whose emitter-collector circuit is connected between the touch plate or switch keys and an input to a comparator. A second transistor and a capacitor are interconnected with the first transistor to provide transient surge protection. The circuits distinguish between differing values of current and activate the comparator which produces a signal indicative of the existing condition.

Current sensing of capacitive keyboard arrays

A vacuum filter for vacuum flow filtration through a filter bed of water from a swimming pool is provided, comprising an open-top tank; a filter bed of particulate material in the tank; fluid flow connections communicating the tank with a water recirculation system for the swimming pool, one adjacent an upper portion and one adjacent a lower portion of the filter bed; an inlet line communicating the swimming pool with the tank and maintaining the level of water in the tank at a level corresponding to a level of water in the swimming pool, thereby providing a head of water for gravity backwash flow through the filter bed, and valves controlling flow into the tank via the fluid flow connections between the tank and the inlet line, and between the tank and the water recirculation system; and a direct fluid flow connection communicating a gutter drain of the swimming pool with the tank; a vacuum is drawn downstream of the filter bed by a pump recirculating filtered water to the swimming pool. In a preferred embodiment, the tank has a dividing wall extending across the tank and separating the tank into first and second compartments; a filter bed of particulate material in the second compartment; two fluid flow connections communicating the two compartments, one adjacent an upper portion and one adjacent a lower portion of the filter bed; two fluid flow connections communicating the second compartment with a water recirculation system for the swimming pool, one adjacent an upper portion and one adjacent a lower portion of the filter bed; an inlet line communicating the swimming pool with the first compartment and maintaining the level of water in the first compartment at a level corresponding to the level of water in the swimming pool, thereby providing a head of water for gravity backwash flow through the filter bed.

Vacuum filter for swimming pools

A liquid level sensing device is provided comprising, in combination, a U-tube having two substantially vertical legs in fluid interconnection at their lower ends; a variable capacitor in one leg of the U-tube, comprising two spaced electrodes receiving a dielectric liquid therebetween; a first mobile body in said one leg of a first dielectric liquid capable of rising and falling within the space between the electrodes and to a level at which it partially or fully fills the space; a second mobile body in said one leg of a second liquid having a higher density than and immiscible with the dielectric liquid, and having an upper surface on which rests the first body of dielectric liquid; a third mobile body in the second leg of a third liquid immiscible with the second liquid and disposed in operative relationship with the second body of liquid; and a fluid pressure communication between said third body and a fourth body of the same or different liquid whose liquid level is to be sensed, so that the relative level of said first body of first liquid in the space between the electrodes in the variable capacitor is related to liquid level in said fourth body, communicated as fluid pressure via the fluid pressure communication to said third body, and thereby moving the second body of liquid and the first body of liquid in the U-tube to a level related to liquid level in said fourth body and corresponding to a capacitance of the variable capacitor.

Growing community of inventors

Garland, TX, United States of America

Frederick G Wall