International Business Machines Corporation

Other

Infineon Technologies Ag

Infineon Technologies North America Corp.

Franz X Zach

Ying Di Zhang

Robert C Wong

Maheswaran Surendra

An L Steegen

Hsing-Jen C Wann

Stephan Kudelka

Hiroyuki Akatsu

Wolfgang Bergner

Rebecca D Mih

Alan C Thomas

Thomas S Rupp

Linda A Chen

Steffen Schulze

A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Selective silicon-on-insulator isolation structure and method

An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

Method for interlayer and yield based optical proximity correction

A system, method and program product that implement a design object that automatically provides compliance to alternating phase shifted mask (altPSM) rules are disclosed. The invention implements a design object that is used during layout to indicate a phase-shiftable design feature in the layout. Each design object includes a base shape indicative of the feature to be ultimately created and two different type phase shape identifiers that identify the requisite mask area and color of phase-shift required for that base shape. Each phase shape identifier is assigned to a portion of the base shape. During layout, overlapping placement of design objects is not allowed if the placement requires overlapping phase identifiers of the same type. Alternatively, placement is allowed where the phase identifiers of different type are separated by a minimum distance from each other defined by a buffer of the design object.

Alternating phase-shift mask rule compliant IC design

Damage to the rim of a semiconductor wafer caused by etching processes is reduced by forming a rim of photoresist or other material around the outer edge of the wafer that has a thickness such that images projected on the rim are sufficiently out of focus that they do not develop, so that etching takes place only in the interior.

Process to suppress lithography at a wafer edge

A method to self-align a lithographic pattern to a workpiece, the method including the steps of obtaining a workpiece having a predetermined pattern of features; modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified; applying a photoresist material; masklessly exposing the photoresist material; developing the photoresist material, the substantial difference in reflectivity of the two adjacent features causing the developed photoresist material to reveal one adjacent feature but not the other.

Method to self-align a lithographic pattern to a workpiece

The non-uniformity edge effect that can affect the quality of chips near the edge of a semiconductor wafer of various steps in the manufacture of integrated circuits is reduced. This is achieved by increasing the field area exposed by a step and repeat printer only when printing squares for chips located near the wafer edge. As a result there is also printed for processing an additional non-functional area outside the functional area to reduce the non-uniformity effect. This increases throughput of the printing apparatus.

Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices

A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.

Contact and deep trench patterning

A method of making at least one feature on an object having an upper surface, comprising the steps of:

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Wappingers Falls, NY, United States of America

Franz X Zach