Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag

Soitec

Qimonda Flash Gmbh

Other

Infineon Technologies LLC

Infineon Ag

Infenion Technologies Ag

Franz Hofmann

Wolfgang Krautschneider

Josef Willer

Michael Specht

Lothar Risch

Wolfgang Roesner

Richard Johannes Luyken

Till Schl&ouml;sser

Hans Reisinger

Erhard Landgraf

Wolfgang Rösner

Wolfgang Rosner

Till Schloesser

Thomas Schulz

Johannes Kretz

Johannes Luyken

Franz Kreupl

Andrew Graham

Reinhard J Stengl

Emmerich Bertagnolli

Alexander Frey

Dirk Manger

Bernd Goebel

Wolfgang R&ouml;sner

Volker Lehmann

Nicolas Nagel

Gerhard Enders

Christoph Ludwig

Till Schlösser

Armin Kohlhase

Wolfgang Hönlein

Lars Dreeskornfeld

Eve Marie Martin

Karl Hofmann

Martin Städele

Thomas Vogelsang

Martin Staedele

Roland Thewes

Hermann Wendt

Georg Tempel

Martin Franosch

Carlos Mazure

Rainer Bruchhaus

Thomas Mikolajick

Detlev Richter

Paul-Werner Von Basse

Reinhard Gabl

Roman Knoefler

Christian Paulus

Wolfram Wersing

Klaus-Guenter Oppermann

Robert Strenz

Meinrad Schienle

Matthias Schreiter

Stephan Riedel

Wolfgang Hoenlein

Doris Keitel-Schulz

Heribert Geib

Lars Bach

Thomas Melde

Robert Wiesner

Christoph Friederich

Barbara Hasler

Martin Jenkner

Ulrike Gruning

Paul Werner Von Basse

Frank Lau

Bernd Gobel

Petra Schindler-Bauer

Hannes Luyken

R Johannes Luyken

Birgit Holzapfl

Thomas Bohm

Paul-Werner Basse

Björn Eversmann

Hermann Fischer

Karl-Heinz Tietgen

Florian Beug

Thomas-Peter Haneder

Guerkan Ilicali

Emmerich Bertagnoll

Ulrich Dorda

Lothar Risoh

Massimo Atti

Petra Theresia Schindler-Bauer

The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

Antifuse cell comprising program transistor and select transistor arranged on opposite sides of semiconductor layer

The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.

SOI finfet with reduced fin width dependence

This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.

Back gate in select transistor for eDRAM

A biosensor array having a substrate, a plurality of biosensor zones arranged on the substrate, each of which has a first terminal and a second terminal, at least one drive line and at least one detection line, the at least one drive line being electrically insulated from the at least one detection line. In each case the first terminal of each biosensor zone is coupled to precisely one of the at least one drive line and the second terminal of each biosensor zone is coupled to precisely one of the at least one detection line, and at least one of the at least one drive line and at least one of the at least one detection line is coupled to at least two of the biosensor zones. The biosensor array also has a drive unit for providing an electrical drive signal, a detection unit for detecting an electrical detection signal resulting from the electrical drive signal, and a selection unit that couples the drive unit to the drive line of a biosensor zone to be selected and the detection unit to the detection line of the biosensor zone to be selected, whereby the biosensor zone is selected.

Biosensors array and method for operating a biosensor array

The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Fully depleted SOI device with buried doped layer

A sensor arrangement for detecting particles potentially contained in an analyte is disclosed. The arrangement includes a substrate; at least one sensor electrode which is arranged on and/or in the substrate and on which scavenger molecules, which hybridize with particles that are potentially contained in an analyte and are to be detected, are immobilized, electrically charged particles generated by hybridization being detectable on the at least one sensor electrode; and at least one diffusion detection electrode which is arranged in a surrounding region of the at least one sensor electrode and is embodied in such a way that it detects electrically charged particles that are generated by hybridization and can be diffused away by the at least one sensor electrode.

Sensor arrangement comprising an electrode for detecting diffused loaded particles

An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method

An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.

Integrated circuit with stacked devices

A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Semiconductor memory device

A method is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies.

Method for functionalizing biosensor chips

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Integrated circuits having a contact region and methods for manufacturing the same

An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.

Integrated circuit with conductive structures

An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.

Integrated circuit including a vertical transistor and method

An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Integrated circuit including a gate electrode

Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

Integrated circuit having NAND memory cell strings

Growing community of inventors

Munich, Germany

Franz Hofmann