Infineon Technologies Ag

Franz Hoffmann

Josef Willer

Till Schl&ouml;sser

DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F .

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München, Germany

Franz Hoffmann