United States of America As Represented by the Secretary of the Air Force

Westinghouse Electric Corporation

Franklyn C Blaha

James R Cricchi

Marvin H White

Michael D Fitzpatrick

A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer. A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

Radiation hardened drain-source protected MNOS transistor

A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.

MNOS memory transistor having a redeposited silicon nitride gate

An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

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Glen Burnie, MD, United States of America

Franklyn C Blaha