Advanced Micro Devices Corporation

Frank Mauersberger

Paul Raymond Besser

Frederick N Hause

Errol Todd Ryan

William S Brennan

John A Iacoponi

Peter J Beckage

Thomas Werner

Hartmut Ruelke

Joerg Hohage

Axel Preusse

Markus Nopper

Gerd Marxsen

A method of forming a multi-layer stack over a low-k dielectric layer is disclosed, wherein the multi-layer stack provides an improved anti-reflective effect and an enhanced protection of the underlying low-k dielectric material during the chemical mechanical polishing process. The multi-layer stack includes silicon dioxide based sub-layers, which may be formed in a highly efficient, non-expensive plasma enhanced deposition method, wherein the optical characteristics may be adjusted by varying a ratio of silane and nitrogen oxide during the deposition.

Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric

In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches, a surface roughness is created at least on non-patterned regions of the dielectric layer to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.

Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process

In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device. The controller is capable of determining the second material, instructing the controllable light source to deliver light of one of the frequencies in response to the second material, comparing the reflected light to a preselected setpoint, and modifying the polishing process in response to the reflected light exceeding the preselected setpoint.

Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques

A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.

Method for forming openings for conductive interconnects

A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Test structure for providing depth of polish feedback

A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.

Method for forming copper interconnects

A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.

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Radebeul, Germany

Frank Mauersberger