Lam Research Corporation

Cutek Research, Inc.

Frank Lin

Tuqiang Q Ni

Jaroslaw Walery Winniczek

Alan Jeffrey Miller

Camelia Rusu

Kenji Takeshita

Tom K Choi

Qinghua Zhong

Chris Lee

Gowri Kota

Harmeet Singh

Arthur M Howald

Vahid Vahedi

Brian K McMillin

Robert P Chebi

Saurabh J Ullal

Qing Xu

Wan-Lin Chen

Weinan Jiang

Jeff A Bogart

Helene Del Puppo

Lily Zheng

Stephan Lassig

Thomas A Kamp

Chiu H Ting

Chung-Ho Huang

Wenli Z Collison

Seongjun Heo

Conan Chiang

Yoko Yamaguchi Adams

Peter Cho

Erin McDonnell

Tanya Andryushchenko

Jin Hwan Ham

Erin Moore

Dai N Lee

Sang Joon Yoon

A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.

Fabrication of a silicon structure and deep silicon etch with profile control

A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

Method for achieving smooth side walls after Bosch etch process

A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.

Line end shortening reduction during etch

A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.

Method for providing high etch rate

The amount of RF power supplied to a plasma in a vacuum plasma processing chamber is gradually changed on a preprogrammed basis in response to signals stored in a computer memory. The computer memory stores signals so that other processing chamber parameters (pressure, gas species and gas flow rates) remain constant while the gradual change occurs. The stored signals enable rounded corners, instead of sharp edges, to be etched, e.g., at an intersection of a trench wall and base.

Plasma processing method and apparatus with control of plasma excitation power

A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Method to improve profile control and N/P loading in dual doped gate applications

A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.

A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.

200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

Vacuum plasma processor method

A spiral-like multi-turn coil excites a plasma for treating a workpiece in a vacuum plasma processor. In one embodiment two of the turns have a discontinuity. Each discontinuity has a capacitor connected across it. An RF source drives the coil via a matching network, an inductor connected to one coil excitation terminal and a capacitor connected to another coil excitation terminal. The impedances of the inductors and the capacitors at the RF source frequency and the discontinuity locations are such as to cause a standing wave voltage of the coil to have (1) equal and opposite values at the coil terminals, (2) sudden amplitude and slope changes, slope reversals and polarity reversals at each of the discontinuities, and (3) three gradual standing wave voltage polarity reversals, spaced from each other by 120&deg;. Two of the gradual polarity reversals are azimuthally aligned with the discontinuities. In a second embodiment, one turn has a discontinuity having a series capacitor connected across it. A shunt capacitor is connected between the discontinuity and ground.

Plasma excitation coil

A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O -free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

Method of plasma etching organic antireflective coating

200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic; fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

Vacuum plasma processor apparatus and method

An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.

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Fremont, CA, United States of America

Frank Lin