Globalfoundries Inc.

Advanced Micro Devices Corporation

Frank Feustel

Thomas Werner

Kai Frohberg

Carsten Peters

Oliver Aubel

Michael Grillberger

Tobias Letz

Uwe Griebenow

Robert Seidel

Ralf Richter

Peter Baars

Jens Heinrich

Juergen Boemmels

Torsten Huisinga

Jan Hoentschel

Matthias Lehr

Frank G Kuechenmeister

Joerg Hohage

Axel Preusse

Frank Koschinsky

Christian Zistl

Katrin Reiche

Andreas Ott

Kerstin Ruttloff

Heike Berthold

Peter Huebler

Christin Bartsch

Sven Mueller

James Werking

Torsten Schmidt

Thomas Foltyn

Pascal Limbecker

Su Ruo Qing

In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system.

Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities

A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Wafer with improved plating current distribution

A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure

In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures.

Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation

Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.

Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge

In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.

Metallization system of a semiconductor device comprising extra-tapered transition vias

In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

Restricted stress regions formed in the contact level of a semiconductor device

In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses.

Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction

The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Method for increasing penetration depth of drain and source implantation species for a given gate height

Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.

Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging

A method for treating a semiconductor device includes dissolving an inert gas species in a wet chemical cleaning solution and treating a material layer of a semiconductor device with the wet chemical cleaning solution in ambient atmosphere. The inert gas species is oversaturated in the wet chemical cleaning solution in the ambient atmosphere.

Growing community of inventors

Dresden, Germany

Frank Feustel