International Business Machines Corporation

Frank F Fang

George A Sai-Halasz

Kwang K Shih

Bertrand M Grossman

Marc H Brodsky

Dennis James Herrell

Wei Hwang

Bernard S Meyerson

Leroy L Chang

Denny D Tang

James Cleary McGroddy

Hwa N Yu

Roland Y Hung

Richard A Webb

A junction is formed by the establishment of first and second adjacent conductivity regions having a transition therebetween from wide (2D) to narrow (1D) with respect to the electron wavelength at the Fermi level. The electrons in the wide region can be propagated at any of a continuum of energies in two dimensions while, in the narrow region, allowable energies become quantized, forming a potential barrier similar to a junction in a tunnel diode. The junction formed in this manner exhibits a Coulomb blockade effect and can be made to operate alternatively as an extremely small capacitance and a conductance to sequentially transfer single electrons, thus forming a Coulomb blockade gate. The Coulomb blockade gate can be used in an oscillator or in digital counting and memory applications.

2D/1D junction device as a Coulomb blockade gate

A modulation doped base heterojunction bipolar transistor wherein the base is a modulation doped heterojunction formed of a layer of p wide gap semiconductor material and a layer of I narrow gap semiconductor material. The collector/base is formed with n+ narrow gap semiconductor material adjacent to the I region of the base. The emitter is n+ wide gap semiconductor material adjacent to the p wide gap layer of the base. The doping concentration and width of the p region of the base is such that all holes are depleted in that region, and a p type inversion layer is formed in the I narrow gap material at its interface with the p wide gap material. This structure provides a modulation doped base heterojunction bipolar transistor which exhibits low base resistance, enhanced performance at low temperatures, a built-in drift field, a reduced emitter injection barrier, no minority carrier storage effects in the base region, and a built-in hot electron effect.

Modulation doped base heterojunction bipolar transistor

A homojunction bipolar transistor having a superlattice base region comprising alternate layers of extrinsic and intrinsic layers, with extrinsic layers being of the opposite conductivity of the emitter and collector layers of the transistor. The alternate extrinsic and intrinsic layers have substantially different doping levels providing abrupt transitions in the valence and conduction bands between layers. The abrupt transitions result in the energy band gap in the base region being effectively reduced with respect to the band gap in the emitter region. In one embodiment, the effective narrow band gap base transistor is implemented by converting a portion of the upper layers of the superlattice to a homogeneous region by heavily doping the portion to form the emitter of the transistor.

Effective narrow band gap base transistor

Apparatus for a bipolar active semiconductor magnetic field sensor that has a higher sensitivity than semiconductor field sensors presently existing in the art. Specifically, the inventive sensor utilizes a semiconductor structure containing a single emitter layer, a single base layer that is overlaid over the emitter layer and two separate oppositely situated collectors located above the base layer. A bias lateral majority carrier flow is established, in preferably and respectively both the base and emitter layers (electrons in the emitter, holes in the base), that flows in opposite directions in these layers and is oriented normal (transverse) both to the direction of transistor current and to the direction of a magnetic field that is to be detected. When the magnetic field is applied to the sensor, this field imparts a Lorentz force to these carriers which causes these majority carriers to deflect in the same direction in both the emitter and base layers, respectively. The resulting deflection of these carriers, in turn, produces local Hall effect voltages, that are proportional to the strength of the magnetic field, across the emitter-base junction that locally increases the forward bias of this junction near one collector and locally decreases the forward bias of this junction near the other collector so as to exponentially increase the collector current flowing through one collector while exponentially decreasing the collector current flow through the other collector. Inasmuch as the exponential collector current flow is a very sensitive function of emitter-base voltage, the inventive sensor is substantially more sensitive than semiconductor sensors known in the art.

Double carrier deflection high sensitivity magnetic sensor

A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

Short channel MOSFET

A thin film transistor technology where a gate member on a substrate surface is in electric field influenceable proximity to active semiconductor devices in the direction normal to the substrate surface and the ohmic electrodes of the active device are parallel with the substrate surface. The gate is formed on the substrate and conformal coatings of insulator and semiconductor are provided over it. A metal is deposited from the direction normal to the surface that is thicker in the horizontal dimension than the vertical so as to be susceptible to an erosion operation such as a dip etch which separates the metal into self-aligned contact areas on each side of a semiconductor device channel without additional masking. Self-alignment of the source, drain and gate can be achieved by insulator additions above and under the gate fabricated without additional masking.

Amorphous thin film transistor device

A construction process employs an insulating abutment which serves as a guide in the formation of a shortlength electrode in the fabrication of a semiconductor device. The process is particularly useful in construction of extremely short channel asymmetric lightly doped drain (LDD) silicon FET's in which case a bird beak is formed on the surface of a silicon wafer. The bird beak is composed of silicon dioxide produced by oxidation of the silicon substrate with the aid of an oxidation resistant covering of silicon nitride, the edge of which defines the location of the abutment. Reactive ion etching is employed to remove excess silicon dioxide leaving a vertical wall at one side of the abutment. Thereafter, the silicon nitride layer is stripped off leaving a slating roof to the abutment. A dope polysilicon layer is deposited conformally on the surface of the substrate and on the abutment to a depth equal to the desired length of the electrode. Further reactive ion etching removes all of the polysilicon except for the portion thereof appended to the vertical wall of the abutment. Thereafter, ion implantation establishes a drain region at the side of the abutment having the slanting roof and a source region at the side of the abutment facing the vertical wall. The profile of the ion implantation follows the profile of the abutment enabling the stopping properties of the abutment to constrict the amount of charge implanted in the drain side of the channel.

Construction of short-length electrode in semiconductor device

A semiconductor structure is provided with progressively changing band gap in a plurality of stages each at an abrupt interface with an asymmetry in the band gap widths such that the major difference in energy gap discontinuity is in the band favoring a particular type of carrier. The transition regions between the progressive material sections are smaller than the carrier mean free path so as to provide kinetic energy for efficient carrier multiplication with reduced noise as the carriers traverse through the device.

Photomultiplier

The combined use of an angularly deposited mask with a subsequent angular conductivity conversion operation extending partially under the mask permits both shorter dimensions and the ability to accommodate the straggle location change when subsequent processing steps occur. The mask is deposited at a low angle with respect to a planar surface, a subsequent conductivity conversion, such as ion implantation, extends under the mask, the mask is removed and a smaller gate is positioned in its location, the gate being smaller than the distance from the source to the point where the conversion extended under the mask, providing thereby an ultra-short gate FET.

Method of making ultrashort FET using oblique angle metal deposition and

A digital photodetector circuit having a photosensing stage connected to a depletion mode field effect transistor forming an inverter stage, increased sensitivity is achieved by then coupling the output of the photo inverter to a second photo inverter whose photosensitive element serves as the active load of an enhancement mode field effect transistor in the inverter stage. The circuit is readily fabricated in integrated structures. The circuit performance may be adjusted for responsiveness to light sensitivity and to provide selectable electrical output signal level and impedance matching including bistable performance.

Digital photodetectors

A semiconductor inversion layer transistor which is compatible with semiconductor fabrication technology, and an integrated circuit which incorporates a plurality of such transistors. In one embodiment of the transistor, a P type indium arsenide base and a P type gallium antimonide emitter are used while the collector can be made of either P type gallium antimonide or N type indium arsenide. By the nature of the band alignment at the interface, the indium arsenide base has its Fermi level pinned in the conduction ban at the base-emitter junction and an assymetrically conducting charge barrier which is formed at this junction is preferential to injection of carriers flowing from the emitter to the base rather than vice versa. When the base-emitter junction is forward biased the electrons at the junction are projected across the base with minimal hole injection from base to emitter, thus providing a high gain transistor having excellent high frequency characteristics.

Semiconductor inversion layer transistor

A MOSFET which is capable of being placed in two states, one of which is quasi-stable and a memory cell which includes such a device is disclosed. The device basically consists of a pair of diffusions of one conductivity type disposed in a substrate of opposite conductivity type. The channel region between the diffusions is ion implanted or diffused with a dopant which forms a channel of the same conductivity type as the diffusions. A gate electrode is spaced from the channel region by a thin oxide and the gate and substrate are biased so that two states of the device are possible. One is a stable, equilibrium or conducting state wherein an opposite conductivity type inversion layer is formed at the surface of the now buried channel. Another state is a quasi-stable, nonequilibrium, nonconductive state wherein the channel region between the diffusions is depleted of mobile charge carriers. This latter state, after a relatively long period of time in the order of several minutes to hours, decays to the stable or conducting state. By applying appropriately poled pulses to the gate or source of the device, the device may be switched from one of the two conducting states to the other. A dynamic memory cell which includes an addressing FET utilizes the device described above. A word line is connected to the gate of an addressing FET which utilizes as its drain the source of the storage device described above while a bit line is connected to the source of the addressing FET. The latter, when rendered conductive by a potential on its gate, applies appropriate write pulses from a pulsed source to place the storage device in one of its two possible states. One embodiment utilizes an annular or enclosed channel device while a memory cell embodiment utilizes an open channel device, the surface of the channel of which is isolated from the substrate by a surrounding recessed oxide (ROX). The channel surface isolation of the storage device is a requirement without which leakage from substrate to the surface would not permit the achievement of the two states of the device. The quasi-stable state remains for a time which is sufficient for most memory purposes and, to the extent that longer times are required, refreshing of the states is available.

Nondestructive read-out dynamic memory cell

The overall performance of integrated circuit systems is enhanced by the use of optical drivers and receivers to send and receive information between the devices on the chip and between individual chips in a system. A single substrate of gallium arsenide employs both the high carrier mobility properties and the electrooptical signal conversion properties on a single substrate to provide both high performance electrical properties and high density and high performance communication properties.

Electrooptical integrated circuit communication

Multicolor light emitting diode arrays can be made using a binary semiconductor substrate on which is grown a graded epitaxial region of an AB.sub.1-x C.sub.x semiconductor. Diodes emitting various light colors can selectively be formed in different regions of the gradient by etching away a portion of the graded region. Arrays of colored light emitting diodes can be made by the techniques of diffusion and selective etching of the graded material.

Growing community of inventors

Yorktown Heights, NY, United States of America

Frank F Fang