Ciena Corporation

Teraxion Inc.

François Pelletier

Christine Latrasse

Yves Painchaud

Michel Poulin

Charles Baudot

Sean Sebastian O'Keefe

Simon Savard

Michael Vitic

Marie-Josée Picard

Antoine Bois

Benoît Filion

Tom M Luk

Alexandre Delisle-Simard

Pierre Bernard

Raphael Beaupré-Laflamme

Claude Gamache

Richard L Lachance

Martin Pelletier

Philippe Pépin

Tristan Rüthers

Louis-Philippe Bibeau

Guillaume Robidoux

Martin Lapointe

Sean Sebastian O'keefe

One or more photonic structures are formed within one or more layers over a surface of a substrate, and multiple trenches are formed through the one or more layers housing devices coupled to one or more of the photonic structures. The trenches may include: a first trench that has a bottom surface within the substrate that has a first surface topology characterized by a first surface roughness at a first depth within the substrate relative to the surface of the substrate, and a second trench that has a bottom surface within the substrate that has a second surface topology characterized by a second surface roughness at a second depth within the substrate relative to the surface of the substrate. The first surface roughness may be greater than the second surface roughness, and the second depth may be greater than the first depth.

Managing trench depth in integrated systems

Aspects of the subject disclosure may include, for example, a process that provides a semiconductor substrate and forms repeating, conductive patterns configured for coupling to active circuitry. Each pattern comprises a group of thermally conductive layers, wherein the group of thermally layers is thermally coupled to a thermal source generated by the active circuitry. Thermally conductive vias interconnect the group of thermally conductive layers, wherein a combination of the vias and the group of thermally conductive layers is configured to transfer heat from the thermal source with a desired directionality. The first repeating patterns are thermally coupled to each other to combine the desired directionality of each of the patterns, wherein the combination results in a distributed directionality of the heat from the thermal source thereby reducing a localized concentration of the heat. Other embodiments are disclosed.

Method and apparatus for managing heat distribution in a semiconductor device

A method including disposing a structural adhesive onto an elevated surface of a first chip that includes a cavity disposed below the elevated surface. The method includes contacting a carrier with the structural adhesive. The carrier includes a second chip that optically aligns with a lateral surface of the cavity. The method includes curing the structural adhesive so that the carrier and host chip are mechanically anchored. An apparatus includes a first chip including a cavity located between lateral walls of the first chip and a carrier mechanically anchored with the first chip at a top portion of the lateral walls. The carrier includes a second chip that optically aligns with the first chip at a side portion of one of the lateral walls. The first and second chips are free of contact at a bottom surface of the second chip and a bottom surface of the cavity.

Enhanced thermal control of a hybrid chip assembly

A coherent receiver includes a receive signal path including i) an input configured to connect a receive signal, ii) one or more signal paths connected to the input and to one or more optical hybrids, and iii) a variable optical attenuator (VOA) in each of the one or more signal paths; and a local oscillator (LO) signal path including i) an input configured to connect to an LO and the one or more optical hybrids, and ii) one or more complementary VOAs located between the input and the one or more optical hybrids, wherein the one or more complementary VOAs are configured to cancel any phase changes from the VOA in each of the one or more signal paths. The VOA in each of the one or more signal paths and the one or more complementary VOAs can be p-i-n junctions.

Coherent receiver having low VOA-induced phase changes

At least a portion of an integrated circuit wafer includes at least one layer in which two or more waveguides are formed. A cavity is formed in the integrated circuit wafer. At least one die, comprising a photonic integrated circuit, has: at least one edge on which there are two or more optical mode defining structures in proximity to respective optical mode defining structures on at least one surface of the cavity, a bottom surface secured to a bottom surface of the cavity, and a top surface on which there is at least one metal contact.

Companion and host chip photonic integration

Fabricating a photonic integrated circuit includes fabricating structures in one or more silicon layers. At least a first silicon layer comprises: one or more photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and one or more light absorbing structures, where at least some of the light absorbing structures include doped silicon. Fabricating the photonic integrated circuit also includes fabricating at least one waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

Managing stray light absorption in integrated photonics devices

A photodetector circuit is disclosed. The photodetector circuit includes an optical input configured to receive a source optical signal for detection by the photodetector circuit, an optical waveguide for coupling the optical input and at least one side of a plurality of sides of a photodiode, wherein the optical waveguide is configured to generate a first optical signal and a second optical signal from the source optical signal, and the photodiode coupled to the first optical waveguide, where the photodiode is illuminated on the at least one side by the first and second optical signals at different locations on the photodiode, where the photodiode generates a photocurrent based on the first and second optical signals reducing photocurrent saturation. Providing a delay between the first and second optical signals reduces an out-of-band frequency response of the photodiode circuit.

Photodetector circuit with improved saturation current and integrated optical filtering

A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.

Flip-chip high speed components with underfill

Systems and methods for non-hermetic Semiconductor Optical Amplifier (SOA) integration on a Silicon photonic (SiP) chip using Complementary Metal-Oxide-Semiconductor (CMOS) processes include creating a trench for placement of the SOA, wherein the trench is between two Spot Size Converters (SSCs) located on the SiP chip outside of the trench; forming pedestals in the trench in one or more existing CMOS layers of the SiP chip to guide vertical alignment of the SOA with the SSCs during its placement; and depositing metallic traces and a solder pattern in the trench above the pedestals to enable the SOAs to electrically bond and rest on the pedestals during reflow.

Non-hermetic semiconductor optical amplifier integration on silicon photonics

An integrated silicon-based photo-detection system, fabricated in an integrated silicon based structure on a silicon-on-insulator (SOI) wafer, includes a photodiode fabricated on an isolated area surrounded by a light barrier, where the light barrier is an area where the SOI wafer is removed, an optical waveguide that guides an input signal light into the photodiode, and external electrical traces that the free electron carriers flow into as photocurrent. A method of fabricating an integrated silicon-based photo-detection system in an integrated silicon based structure on a silicon-on-insulator (SOI) wafer, includes performing deep etching to create a light barrier surrounding an isolated area on the SOI wafer, fabricating a photodiode in the isolated area surrounded by the light barrier, fabricating an optical waveguide that guides an input signal light into the photodiode, and wirebonding external electrical traces to connect to the remainder of the integrated silicon based structure.

Optically isolated photodiode for high sensitivity application

A connectorized optical chip assembly connectable to an external optical fiber having a fiber connector is provided. The connectorized optical chip assembly includes a substrate, an optical chip having an on-chip optical waveguide and a connectorized interface. The connectorized interface includes an optical coupling element mounted in optical alignment with the on-chip optical waveguide. The connectorized interface includes a chip connector engaging the optical coupling element and configured for mating with the fiber connector of the external optical fiber, so as to provide an optical coupling of light between the optical coupling element and the external optical fiber. The connectorized optical chip assembly also includes a mechanical support structure supporting the connectorized interface onto the substrate. Preferably, the components of the connectorized optical assembly are made of materials heat resistant to temperatures used to melt solder in surface mount processes.

Connectorized optical chip assembly

An optical system may include a substrate that includes an etched region and a laser-induced breakage region. The optical system may further include an optical waveguide disposed on the substrate. The optical system may further include an optical device coupled to the optical waveguide within the etched region. The laser-induced breakage region may produce a predetermined coupling gap between the optical waveguide and the optical device.

Optical coupling surface fabrication

A post-assembly wavelength-tuning method for an optical filter provided along an optical fiber mounted under tension in a packaging assembly is provided. The packaging assembly includes at least one packaging component mechanically coupled to the optical fiber and optically accessible from outside of the packaging assembly. The method includes a step of measuring a post-assembly spectral response of the optical filter and determining therefrom a spectral deviation with respect to a target spectral response. The method also includes a step of forming one or more laser-welded zones on the packaging component so as to cause a permanent deformation thereof. The permanent deformation induces a modification in length of the optical fiber, thereby changing the post-assembly spectral response of the optical filter to compensate for the measured spectral deviation.

Post-assembly wavelength-tuning method for an optical fiber filter

An optical coupling assembly for coupling light from an optical fiber including an angled tip into a planar waveguide via a waveguide coupling element is provided. In one embodiment, the optical fiber extends along the planar waveguide with the angled tip positioned such that light propagating in the optical fiber is coupled by the waveguide coupling element to propagate in the planar waveguide in counter propagation with respect to a fiber propagation direction. In another embodiment, the optical fiber includes a tapered peripheral portion tapering toward the angled tip and is disposed over the planar waveguide with the tapered peripheral portion extending therealong such that light propagating in the optical fiber is coupled to propagate in the planar waveguide with either forward or counter propagation. Embodiments of the present invention may be part of various photonic integrated circuits and may be manufactured more easily than known optical coupling assemblies.

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François Pelletier