Intersil Americas Inc.

Magnachip Semiconductor, Inc.

National Semiconductor Corporation

Spectrian Corporation

Linear Technology Corporation

Globalfoundries U.S. Inc.

Alpha Omega Semiconductor Inc.

Cree Gmbh

Soitec

Cree Microwave, Inc.

Fultec Semiconductor, Inc.

Hewlett-Packard Company

Bourns Incorporated

Avantek, Inc.

National Semiconductor Corportaion

Francois Hebert

Rashid Bashir

Datong Chen

Daniel Ng

Seong Min Choe

Rick Carlton Jerome

Shekar Mallikarjunaswamy

Dev Alok Girdhar

Young Bae Kim

Richard A Harris

Yon Sup Pang

Craig McLachlan

Seong Min Cho

Kevin Hoopingarner

Ju Ho Kim

Jin Woo Moon

I-Shan Sun

Anup Bhalla

Nikhil Vishwanath Kelkar

Pablo Eugenio D'Anna

Handoko Linewih

Young Joon Kim

Kang Sup Shin

John F Sevic

Jong Yeul Jeong

Yu Shin Ryu

Hee Baeg An

Michael W Althar

Seong Woo Lee

Peter Oaklander

Eric S Lee

Steven R Rivet

William H McCalpin

David B Bell

Szehim Ng

Michael I-Shan Sun

Sze Him Ng

John J Ellis-Monaghan

Steven J Bentley

Michael Joseph Zierak

Mark Levy

Izak Bencuya

Johnatan A Kantarovsky

James Albert Cooper, Jr

Kwang Il Kim

Stephen Joseph Gaul

Kyung Ho Lee

Sze-Hon Kwan

Stephen S Coates

Abul Ehsanul Kabir

Kwangil Kim

In Taek Oh

Young Ju Kim

Ihl Hyun Cho

Intaek Oh

Jinwoo Moon

Szehim Daniel Ng

Youngbae Kim

Lawrence Selvaraj Susai

Youngju Kim

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer in the trench, and a dielectric layer on the top surface of the semiconductor substrate. The dielectric layer includes an opening that is aligned with the trench in the semiconductor substrate, and the dielectric layer comprises a material with a melting point that is greater than or equal to 2000° C.

Field-effect transistors with a high-temperature hardmask and self-aligned p-shield

Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

Monolithic integration of diverse device types with shared electrical isolation

Structures for a junction field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a trench, and a source including a doped region in the semiconductor substrate adjacent to the trench. The doped region and the semiconductor substrate have the same conductivity type. The doped region has a first boundary adjacent to a surface of the semiconductor substrate and a second boundary spaced in depth from the first boundary. The structure further comprises a gate structure including a conductor layer inside the trench and a dielectric layer inside the trench. The first conductor layer has a surface positioned between the first boundary of the doped region and the second boundary of the doped region, and the dielectric layer is positioned on the surface of the conductor layer.

Junction field-effect transistors implemented in a wide bandgap semiconductor material

The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

Multi-channel transistor

Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode.

Bidirectional switches with active substrate biasing

A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

Semiconductor device having circuitry positioned above a buried magnetic sensor

Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Low-cost semiconductor device manufacturing method

A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

Semiconductor device with schottky diode and manufacturing method thereof

Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Back-to-back stacked dies

A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Lateral PNP bipolar transistor with narrow trench emitter

A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing are comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Semiconductor package

The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.

Photo sensor module

Growing community of inventors

San Mateo, CA, United States of America

Francois Hebert