Altera Corporation

Francois Gregoire

Peter John McElheny

Yowjuang (Bill) Liu

Jayakannan Jayapalan

Yow-Juang (Bill) Liu

Priya Selvaraj

Raminda U Madurawe

Bill Yowjuang Liu

Guru Thalapaneni

Yow-Juang(Bill) W Liu

The present invention is a novel method whereby voids or solid opens at the bottom of via can be avoided without drastically altering the resistivity or parasitic capacitances of the whole metal interconnect system. The invention includes in one embodiment a process of forming interconnects and vias in a microelectronic circuit structure. This process includes implanting and/or alloying an impurity element in the local area of the top surface of a metal interconnect at the bottom of a via. Doping may be done before or after formation of the via. After the via is formed, it is filled with a metal such as copper. Another embodiment of the invention is a microelectronic circuit structure manufactured by the aforementioned method.

Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via

A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.

Polysilicon gate doping level variation for reduced leakage current

The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present invention includes a gate, source/drain diffusion regions on opposite sides of the gate, and source/drain extensions adjacent the source/drain diffusion regions. The MOSFET also includes at least one added corner diffusion region that overlaps with at least a portion of a source/drain extension region for reducing off-state leakage currents. The corner diffusions can be created using conventional CMOS IC fabrication processes with some modification of an ion implant mask used in manufacturing a conventional CMOS IC.

Field effect transistor with corner diffusions for reduced leakage

Advanced MOSFET design

A capacitive electrode structure for use in an integrated circuit fabricated on a substrate comprises a first electrode formed by a diffusion region in the substrate, an insulating layer formed on the diffusion region, and a second electrode formed by a conductive layer deposited on said insulating layer. To increase the capacitance per chip area of the capacitive electrode structure, a plurality of recesses are formed in the first electrode on an upper surface thereof with a lower surface of the second electrode substantially following a contour of these recesses. In one embodiment, the capacitive electrode structure is employed for a capacitor formed between a control gate and a floating gate in an EEPROM cell. Capacitors in other types of integrated circuit can be likewise formed using the electrode structure of the present invention. Preferably, the recesses in the diffusion region are formed concurrently with oxide-filled isolation trenches in the substrate used to isolate adjacent circuit elements from each other.

High performance capacitor structure

A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.

Pad structures for an integrated circuit are provided that use via holes or slots rather than large pad openings to form electrical connections between successive metal interconnection layers. The via holes or slots are filled using standard metal etchback deposition techniques. The pad structures minimize particle generation during circuit fabrication. A number of the via holes or slots in the pad structure can be interconnected in parallel to provide a sufficient current handling capacity to distribute power to the active components on the integrated circuit.

Growing community of inventors

Cupertino, CA, United States of America

Francois Gregoire